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MC100E137

8-BIT RIPPLE COUNTER

Description TheMC10E/100E137isaveryhighspeedbinaryripplecounter.ThetwoleastsignificantbitsweredesignedwithveryfastedgerateswhilethemoresignificantbitsmaintainstandardECLinPS?outputedgerates.Thisallowsthecountertooperateatveryhighfrequencieswhilemaintain

MC100E137

MC100E137: ECL 8-Bit Ripple Counter; Differential Clock Input and Data Output Pins\nVBB Output for Single-Ended Use\nSynchronous and Asynchronous Enable Pins\nAsynchronous Master Reset\nPECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V\nNECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V\nInternal Input Pulldown Resistors\nESD Protection: > 2 KV HBM, > 100 V MM\nMeets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test\nMoisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D\nFlammability Rating: UL-94 code V-0 @ 1/8\", Oxygen Index 28 to 34\nTransistor Count = 330 devices\nPb-Free Packages are Available\n;

The MC10E/100E137 is a very high speed binary ripple counter. The two least significant bits were designed with very fast edge rates while the more significant bits maintain standard ECLinPS output edge rates. This allows the counter to operate at very high frequencies while maintaining a moderate power dissipation level.The device is ideally suited for multiple frequency clock generation as well as a counter in a high performance ATE time measurement board. Both asynchronous and synchronous enables are available to maximize the device's flexibility for various applications. The asynchronous enable input, A_Start, when asserted enables the counter while overriding any synchronous enable signals. The E137 features XORed enable inputs, EN1 and EN2, which are synchronous to the CLK input. When only one synchronous enable is asserted the counter becomes disabled on the next CLK transition; all outputs remain in the previous state poised for the other synchronous enable or A_Start to be asserted to re-enable the counter. Asserting both synchronous enables causes the counter to become enabled on the next transition of the CLK.If EN1 (or EN2) and CLK edges are coincident, sufficient delay has been inserted in the CLK path (to compensate for the XOR gate delay and the internal D-flip flop setup time) to insure that the synchronous enable signal is clocked correctly, hence, the counter is disabled. The E137 can also be driven single-endedly utilizing the VBB output supply as the voltage reference for the CLK input signal.If a single-ended signal is to be used the VBB pin should be connected to the CLKbar input and MR bypassed to ground via a 0.01 uF capacitor. VBB can only source/sink 0.5mA, therefore it should be used as a switching reference for the E137 only. All input pins left open will be pulled LOW via an input pulldown resistor. Therefore, do not leave the differential CLK inputs open. Doing so causes the current source transisto

MC100E137

5 V ECL 8-Bit Ripple Counter

MC100E137

5 VECL 8-Bit Ripple Counter

MC100E137FN

5 V ECL 8-Bit Ripple Counter

MC100E137FN

5 VECL 8-Bit Ripple Counter

MC100E137FNG

5 V ECL 8-Bit Ripple Counter

MC100E137FNG

5V ECL 8??it Ripple Counter

MC100E137FNG

5 VECL 8-Bit Ripple Counter

MC100E137FNR2

5 V ECL 8-Bit Ripple Counter