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M48Z58Y-70PC1TR中文資料意法半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

廠商型號 |
M48Z58Y-70PC1TR |
功能描述 | 64 Kbit 8Kb x 8 ZEROPOWER SRAM |
文件大小 |
133.81 Kbytes |
頁面數(shù)量 |
17 頁 |
生產(chǎn)廠商 | STMICROELECTRONICS |
中文名稱 | 意法半導(dǎo)體 |
網(wǎng)址 | |
數(shù)據(jù)手冊 | |
更新時間 | 2025-9-1 8:01:00 |
人工找貨 | M48Z58Y-70PC1TR價格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
M48Z58Y-70PC1TR規(guī)格書詳情
描述 Description
The M48Z58/Y ZEROPOWER? RAM is an 8 Kbit x 8 non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory solution.
特性 Features
■ Integrated, ultra low power SRAM, power-fail control circuit, and battery
■ READ cycle time equals WRITE cycle time
■ Automatic power-fail chip deselect and WRITE protection
■ WRITE protect voltages: (VPFD = power-fail deselect voltage)
– M48Z58: VCC = 4.75 to 5.5 V; 4.5 V ≤ VPFD ≤ 4.75 V
– M48Z58Y: VCC = 4.5 to 5.5 V; 4.2 V ≤ VPFD ≤ 4.5 V
■ Self-contained battery in the CAPHAT? DIP package
■ Packaging includes a 28-lead SOIC and SNAPHAT? top (to be ordered separately)
■ SOIC package provides direct connection for a SNAPHAT? top which contains the battery
■ Pin and function compatible with JEDEC standard 8 Kbit x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
AMD |
24+ |
BGA |
12 |
原裝現(xiàn)貨假一罰十 |
詢價 | ||
ST |
25+23+ |
DIP |
29212 |
絕對原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢價 | ||
AMD |
24+ |
BGA |
880000 |
明嘉萊只做原裝正品現(xiàn)貨 |
詢價 | ||
AD |
23+ |
DIP |
9827 |
詢價 | |||
ST |
25+ |
PCDIP-28 |
3200 |
全新原裝、誠信經(jīng)營、公司現(xiàn)貨銷售! |
詢價 | ||
ST/意法 |
2407+ |
DIP |
7750 |
原裝現(xiàn)貨!實(shí)單直說!特價! |
詢價 | ||
24+ |
3000 |
公司存貨 |
詢價 | ||||
AMD |
23+ |
BGA |
5000 |
原裝正品,假一罰十 |
詢價 | ||
AMD |
2447 |
BGA |
100500 |
一級代理專營品牌!原裝正品,優(yōu)勢現(xiàn)貨,長期排單到貨 |
詢價 | ||
ST |
22+ |
DIP |
25000 |
只有原裝絕對原裝,支持BOM配單! |
詢價 |