特性 Features

? JEDEC Standard

? Internal pipelined double-data-rate architecture, two data access per clock cycle

? Bi-directional data strobe (DQS)

? On-chip DLL

? Differential clock inputs (CLK and CLK )

? DLL aligns DQ and DQS transition with CLK transition

? Quad bank operation

? CAS Latency : 2, 2.5, 3

? Burst Type : Sequential and Interleave

? Burst Length : 2, 4, 8

? All inputs except data & DM are sampled at the rising edge of the system clock(CLK)

? Data I/O transitions on both edges of data strobe (DQS)

? DQS is edge-aligned with data for reads; center-aligned with data for WRITE

? Data mask (DM) for write masking only

? For 2.5V parts, VDD = 2.3V ~ 2.7V, VDDQ = 2.3V ~ 2.7V

? Auto & Self refresh

? 64ms refresh period, 4K cycle

? SSTL-2 I/O interface

? 66pin TSOPII and 60 ball BGA package