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LMX1860PAP/EM中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

LMX1860PAP/EM
廠商型號

LMX1860PAP/EM

功能描述

LMX1860-SEP Low-Noise, High-Frequency JESD204B/C Buffer, Multiplier and Divider

絲印標(biāo)識

LMX1860

封裝外殼

HTQFP

文件大小

2.98315 Mbytes

頁面數(shù)量

64

生產(chǎn)廠商 Texas Instruments
企業(yè)簡稱

TI1德州儀器

中文名稱

美國德州儀器公司官網(wǎng)

原廠標(biāo)識
TI1
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-8-2 15:36:00

人工找貨

LMX1860PAP/EM價格和庫存,歡迎聯(lián)系客服免費人工找貨

LMX1860PAP/EM規(guī)格書詳情

1 Features

? VID #V62/24630

– Total ionizing dose 30krad (ELDRS-free)

– Single event latch-up (SEL) immune up to

43MeV - cm2 /mg

– Single event functional interrupt (SEFI) immune

up to 43MeV - cm2 /mg

? Clock buffer for 300MHz to 15GHz frequency

? Ultra-Low Noise

– Noise floor of –159dBc/Hz at 6GHz output

– 36-fs additive jitter (100Hz to fCLK) at 6GHz

output

– 5fs additive jitter (100Hz - 100MHz)

? 4 high-frequency clocks with corresponding

SYSREF outputs

– Shared divide by 1 (Buffer), 2, 3, 4, 5, 6, 7, and

8

– Shared programmable multiplier x2, x3, and x4

? Support pin mode options to configure the device

without SPI

? LOGICLK output with corresponding SYSREF

output

– On separate divide bank

– 1, 2, 4 pre-divider

– 1 (bypass), 2, …, 1023 post divider

? 8 programmable output power levels

? Synchronized SYSREF clock outputs

– 508 delay step adjustments of less than 2.5ps

each at 12.8GHz

– Generator and repeater modes

– Windowing feature for SYSREFREQ pins to

optimize timing

? SYNC feature to all divides and multiple devices

? 2.5V operating voltage

? –55oC to 125oC operating temperature

? High Reliability

– Controlled Baseline

– One Assembly/Test Site

– One Fabrication Site

– Extended Product Life Cycle

– Product Traceability

2 Applications

? Radar imaging payload

? Communications payloads

? Command and data handling

? Data converter clocking

? Clock distribution/multiplication/division

3 Description

The LMX1860-SEP is an buffer, divider and multiplier

that features high frequency, ultra-low jitter, and

SYSREF outputs. This device combined with an ultralow

noise reference clock source is an exemplary

design for clocking data converters, especially when

sampling above 3GHz. Each of the 4 high frequency

clock outputs and additional LOGICLK output is

paired with a SYSREF output clock signal. The

SYSREF signal for JESD interfaces can either be

internally generated or passed in as an input and

re-clocked to the device clocks. This device can

distribute the multichannel, low skew, ultra-low noise

local oscillator signals to multiple mixers by disabling

the SYSREF outputs.

供應(yīng)商 型號 品牌 批號 封裝 庫存 備注 價格
原廠正品
23+
SOP16
5000
原裝正品,假一罰十
詢價
NSC
24+
9990
詢價
NS
25+
SOP-14-3.9mm
3200
全新原裝、誠信經(jīng)營、公司現(xiàn)貨銷售!
詢價
NS/國半
24+
SOP16
9600
原裝現(xiàn)貨,優(yōu)勢供應(yīng),支持實單!
詢價
NS
23+
SOP-16P
9823
詢價
NS
22+
SOP
3000
原裝正品,支持實單
詢價
NSC
2023+
TSSOP-28
50000
原裝現(xiàn)貨
詢價
NSC
2022+
SOP
20000
只做原裝進(jìn)口現(xiàn)貨.假一罰十
詢價
NS
23+
SOP3.9
13000
原廠授權(quán)一級代理,專業(yè)海外優(yōu)勢訂貨,價格優(yōu)勢、品種
詢價
NS/美國國半
24+
SOP
9624
鄭重承諾只做原裝進(jìn)口現(xiàn)貨
詢價