特性 Features

? Memory densities: 15, 30, 60Mbit

? 150MHz Max clock rate

? Independent Read and Write ports:

? Supports simultaneous read/write operations

? Enables buffering across clock domains

? Operating Modes:

? Single-channel FIFO w/ Asynchronous I/O

? Dual independent FIFOs w/ Asynchronous I/O

? Flexible Write/Read Pointer Manipulation

? W/R address pointer Clear/Set

? W/R address pointers can be overridden in real time using external 24bit address port

? TRS detection for auto-clearing of Write pointer

? W/R memory access Enable/Disable

? Input enable control (Write Masking) for freeze frame control

? Selectable I/O VDD = 1.8V, 2.5V, 3.3V

? Selectable Core VDD = 1.8V, 2.5V, 3.3V

? 172 ball FBGA package (15 x 15 x 1.4mm)

? Depth expansion is supported for Multi-frame HDTV, Multiframe SDTV, and other formats:

? Seamless address space is maintained with up to 12 cascaded devices

? Near-Full/Empty Flags With Programmable Thresholds

? Collide Flag alerts User of W/R pointer crossings

? I2C Serial Microprocessor Interface

? Output Enable Control (Data Skipping)

? JTAG Boundary Scan - IEEE 1149.1

Applications

? Frame buffer for common HD formats (720p, 1080i, 1080p)

? HDTV / SDTV Frame Synchronization

? HDTV Display Buffer

? Time Base Correction (TBC)

? Freeze-Frame Buffer

? Picture-in-Picture (PIP) Buffer

? Frame Rate Conversion

? Security Camera Systems

? Field-Based or Frame-Based Comb Filtering

? HD Video Capture & Editing Systems

? Deep Data Buffering

? Image Manipulation (Rotation, Zoom)

? Test Pattern Generation

? Motion Detection or Frame-to-Frame Correlation