KSZ9567R屬于集成電路（IC）的控制器。由微芯科技股份有限公司制造生產(chǎn)的KSZ9567R控制器該系列產(chǎn)品主要用于在采用不同通信協(xié)議和/或信令方法的端點之間提供信息連接。示例包括將 I2C 總線連接到 UART，將 USB 連接到 I2C、SPI、以太網(wǎng)或 UART、以太網(wǎng) MAC 和 PHY 等的器件。此外，還包括用于通過為點對點通信設(shè)計的接口建立多路連接的器件，例如 USB 集線器控制器。

特性 Features

? Switch Management Capabilities

- 10/100/1000Mbps Ethernet switch basic functions:

frame buffer management, address look-up table,

queue management, MIB counters

- Non-blocking store-and-forward switch fabric assures

fast packet delivery by utilizing 4096 entry forwarding

table with 256kByte frame buffer

- Jumbo packet support up to 9000 bytes

- Port mirroring/monitoring/sniffing:

ingress and/or egress traffic to any port

- Rapid spanning tree protocol (RSTP) support for topology

management and ring/linear recovery

- Multiple spanning tree protocol (MSTP) support

? Two Configurable External MAC Ports

- Reduced Gigabit Media Independent Interface

(RGMII) v2.0

- Reduced Media Independent Interface (RMII) v1.2

with 50MHz reference clock input/output optionvm

- Media Independent Interface (MII) in PHY/MAC mode

? Five Integrated PHY Ports

- 1000BASE-T/100BASE-TX/10BASE-Te IEEE 802.3

- Fast Link-up option significantly reduces link-up time

- Auto-negotiation and Auto-MDI/MDI-X support

- On-chip termination resistors and internal biasing for

differential pairs to reduce power

- LinkMD? cable diagnostic capabilities for determining

cable opens, shorts, and length

? Advanced Switch Capabilities

- IEEE 802.1Q VLAN support for 128 active VLAN

groups and the full range of 4096 VLAN IDs

- IEEE 802.1p/Q tag insertion/removal on per port basis

- VLAN ID on per port or VLAN basis

- IEEE 802.3x full-duplex flow control and half-duplex

back pressure collision control

- IEEE 802.1X access control

(Port-based and MAC address based)

- IGMP v1/v2/v3 snooping for multicast packet filtering

- IPv6 multicast listener discovery (MLD) snooping

- IPv4/IPv6 QoS support, QoS/CoS packet prioritization

- 802.1p QoS packet classification with 4 priority queues

- Programmable rate limiting at ingress/egress ports

? IEEE 1588v2 PTP and Clock Synchronization

- Transparent Clock (TC) with auto correction update

- Master and slave Ordinary Clock (OC) support

- End-to-end (E2E) or peer-to-peer (P2P)

- PTP multicast and unicast message support

- PTP message transport over IPv4/v6 and IEEE 802.3

- IEEE 1588v2 PTP packet filtering

- Synchronous Ethernet support via recovered clock

? Audio Video Bridging (AVB)

- Compliant with IEEE 802.1BA/AS/Qat/Qav standards

- Priority queuing, Low latency cut-through mode

- gPTP time synchronization, credit-based traffic shaper

- Time aware traffic scheduler per port

? Comprehensive Configuration Registers Access

- High-speed 4-wire SPI (up to 50MHz), I2C interfaces

provide access to all internal registers

- MII Management (MIIM, MDC/MDIO 2-wire) Interface

provides access to all PHY registers

- In-band management via any of the data ports

- I/O pin strapping facility to set certain register bits from

I/O pins at reset time

? Power Management

- Energy detect power-down mode on cable disconnect

- Dynamic clock tree control

- Unused ports can be individually powered down

- Full-chip software power-down

- Wake-on-LAN (WoL) standby power mode with PME

interrupt output for system wake upon triggered events

Target Applications

? Industrial Ethernet (Profinet, MODBUS, Ethernet/IP)

? Real-time Ethernet networks

? IEC 61850 networks w/ power substation automation

? Industrial control/automation switches

? Networked measurement and control systems

? Test and measurement equipment