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KM44L32031BT-GLZ/Y/0中文資料三星數(shù)據(jù)手冊PDF規(guī)格書
KM44L32031BT-GLZ/Y/0規(guī)格書詳情
特性 Features
? Double-data-rate architecture; two data transfers per clock cycle
? Bidirectional data strobe(DQS)
? Four banks operation
? Differential clock inputs(CK and CK)
? DLL aligns DQ and DQS transition with CK transition
? MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
? All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
? Data I/O transactions on both edges of data strobe
? Edge aligned data output, center aligned data input
? LDM,UDM/DM for write masking only
? Auto & Self refresh
? 15.6us refresh interval(4K/64ms refresh)
? Maximum burst refresh cycle : 8
? 66pin TSOP II package
產(chǎn)品屬性
- 型號：
KM44L32031BT-GLZ/Y/0
- 制造商：
SAMSUNG
- 制造商全稱：
Samsung semiconductor
- 功能描述：
DDR SDRAM Specification Version 1.0
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
SEC |
6000 |
面議 |
19 |
TSOP |
詢價 | ||
SAMSUNG |
23+ |
TSOP54 |
12800 |
##公司主營品牌長期供應(yīng)100%原裝現(xiàn)貨可含稅提供技術(shù) |
詢價 | ||
SAM |
24+/25+ |
131 |
原裝正品現(xiàn)貨庫存價優(yōu) |
詢價 | |||
SAMSUNG |
24+ |
TSOP |
80000 |
只做自己庫存 全新原裝進(jìn)口正品假一賠百 可開13%增 |
詢價 | ||
SAM |
23+ |
NA |
128 |
專做原裝正品,假一罰百! |
詢價 | ||
SAMSUNG |
24+ |
TSOP |
48000 |
特價特價100原裝長期供貨. |
詢價 | ||
SAMSUNG |
24+ |
TSOP-7.2-24P |
2560 |
絕對原裝!現(xiàn)貨熱賣! |
詢價 | ||
SAMSUNG |
9801+ |
TSOP |
348 |
一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價 | ||
SAMSUNG |
23+ |
TSOP |
8560 |
受權(quán)代理!全新原裝現(xiàn)貨特價熱賣! |
詢價 | ||
SAMSUNG |
24+ |
TSOP |
5825 |
公司原廠原裝現(xiàn)貨假一罰十!特價出售!強勢庫存! |
詢價 |
