首頁>K4H280438M-TCA0>規(guī)格書詳情
K4H280438M-TCA0中文資料三星數據手冊PDF規(guī)格書
相關芯片規(guī)格書
更多K4H280438M-TCA0規(guī)格書詳情
特性 Features
? Double-data-rate architecture; two data transfers per clock cycle
? Bidirectional data strobe(DQS)
? Four banks operation
? Differential clock inputs(CK and CK)
? DLL aligns DQ and DQS transition with CK transition
? MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
? All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
? Data I/O transactions on both edges of data strobe
? Edge aligned data output, center aligned data input
? LDM,UDM/DM for write masking only
? Auto & Self refresh
? 15.6us refresh interval(4K/64ms refresh)
? Maximum burst refresh cycle : 8
? 66pin TSOP II package
產品屬性
- 型號：
K4H280438M-TCA0
- 制造商：
SAMSUNG
- 制造商全稱：
Samsung semiconductor
- 功能描述：
128Mb DDR SDRAM
| 供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
SAMSUNG |
22+ |
TSOP |
8000 |
原裝正品支持實單 |
詢價 | ||
SAM |
24+/25+ |
480 |
原裝正品現貨庫存價優(yōu) |
詢價 | |||
SAMSUNG |
24+ |
TSOP |
2789 |
原裝優(yōu)勢!絕對公司現貨! |
詢價 | ||
SAMSUNG/三星 |
22+ |
TSOP |
12245 |
現貨,原廠原裝假一罰十! |
詢價 | ||
專營SAMSUNG |
23+ |
TSSOP |
3500 |
詢價 | |||
Samsung |
NA |
8560 |
一級代理 原裝正品假一罰十價格優(yōu)勢長期供貨 |
詢價 | |||
SAMSUNG/三星 |
22+ |
TSOP |
18000 |
只做全新原裝,支持BOM配單,假一罰十 |
詢價 | ||
SAMSUNG |
6000 |
面議 |
19 |
DIP/SMD |
詢價 | ||
SAMSUNG |
23+ |
TSOP |
5000 |
原裝正品,假一罰十 |
詢價 | ||
SAMSUNG |
2025+ |
TSOP |
3685 |
全新原廠原裝產品、公司現貨銷售 |
詢價 |
