描述 Description

The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032 features 5-Volt insystem programming and in-system diagnostic capabilities. It is the first device which offers non-volatile on-the-fly reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1032 device, but multiplexes four of the dedicated input pins to control in-system programming.

特性 Features

? HIGH-DENSITY PROGRAMMABLE LOGIC

— High Speed Global Interconnect

— 6000 PLD Gates

— 64 I/O Pins, Eight Dedicated Inputs

— 192 Registers

— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

— Small Logic Block Size for Fast Random Logic

— Security Cell Prevents Unauthorized Copying

? HIGH PERFORMANCE E2CMOS? TECHNOLOGY

— fmax = 90 MHz Maximum Operating Frequency

— fmax = 60 MHz for Industrial and Military/883 Devices

— tpd = 12 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile E2CMOS Technology

— 100 Tested

? ispLSI OFFERS THE FOLLOWING ADDED FEATURES

— In-System Programmable? (ISP?) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

? COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue Logic and Structured Designs

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global Interconnectivity

? ispLSI AND pLSI DEVELOPMENT TOOLS

pDS? Software

— Easy to Use PC Windows? Interface

— Boolean Logic Compiler

— Manual Partitioning

— Automatic Place and Route

— Static Timing Table

ispDS+? Software

— Industry Standard, Third Party Design Environments

— Schematic Capture, State Machine, HDL

— Automatic Partitioning and Place and Route

— Comprehensive Logic and Timing Simulation

— PC and Workstation Platforms