OVERVIEW

ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks.

FEATURES

? Clock frequency: 166, 143, 133 MHz

? Fully synchronous; all signals referenced to a positive clock edge

? Internal bank for hiding row access/precharge

? Single Power supply: 3.3V + 0.3V

? LVTTL interface

? Programmable burst length – (1, 2, 4, 8, full page)

? Programmable burst sequence: Sequential/Interleave

? Auto Refresh (CBR)

? Self Refresh

? 4096 refresh cycles every 16ms (A2 grade) or 64 ms (Commercial, Industrial, A1 grade)

? Random column address every clock cycle

? Programmable CAS latency (2, 3 clocks)

? Burst read/write and burst read/single write operations capability

? Burst termination by burst stop and precharge command