FEATURES

? VDD and VDDQ: 2.5V ± 0.2V (-6)

? VDD and VDDQ: 2.6V ± 0.1V (-5)

? SSTL_2 compatible I/O

? Double-data rate architecture; two data transfers

per clock cycle

? Bidirectional, data strobe (DQS) is transmitted/

received with data, to be used in capturing data

at the receiver

? DQS is edge-aligned with data for READs and

centre-aligned with data for WRITEs

? Differential clock inputs (CK and CK)

? DLL aligns DQ and DQS transitions with CK

transitions

? Commands entered on each positive CK edge;

data and data mask referenced to both edges of

DQS

? Four internal banks for concurrent operation

? Data Mask for write data. DM masks write data

at both rising and falling edges of data strobe

? Burst Length: 2, 4 and 8

? Burst Type: Sequential and Interleave mode

? Programmable CAS latency: 2, 2.5 and 3

? Auto Refresh and Self Refresh Modes

? Auto Precharge

? TRAS Lockout Supported (tRAP = tRCD )