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IN74HC112AN

Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS

DualJ-KFlip-FlopwithSetandReset High-PerformanceSilicon-GateCMOS TheIN74HC112AisidenticalinpinouttotheLS/ALS112.ThedeviceinputsarecompatiblewithstandardCMOSoutputs;withpullupresistors,theyarecompatiblewithLS/ALSTTLoutputs. Eachflip-flopisnegative-edg

IN74HC112AN

Dual J-K Flip-Flop with Set and Reset;

Dual J-K Flip-Flop with Set and Reset\nHigh-Performance Silicon-Gate CMOSThe IN74HC112A is identical in pinout to the LS/ALS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.\nEach flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs.? Outputs Directly Interface to CMOS, NMOS, and TTL\n? Operating Voltage Range: 2.0 to 6.0 V\n? Low Input Current: 1.0 μA\n? High Noise Immunity Characteristic of CMOS Devices

IN74HC112AN/AD

Dual J-K Negative-Edge-Triggered Flip-Flop;

KK74HC112A

DualJ-KFlip-FlopwithSetandResetHigh-PerformanceSilicon-GateCMOS

KK74HC112AD

DualJ-KFlip-FlopwithSetandResetHigh-PerformanceSilicon-GateCMOS

KK74HC112AN

DualJ-KFlip-FlopwithSetandResetHigh-PerformanceSilicon-GateCMOS

M74HC112

DUALJ-KFLIPFLOPWITHPRESETANDCLEAR

M74HC112

DUALJ-KFLIPFLOPWITHPRESETANDCLEAR

DESCRIPTION TheM54HC112isanhighspeedCMOSDUALJ-KFLIP-FLOPWITHPRESETANDCLEARfabricatedwithsilicongateC2MOStechnology. TheM54HC112dualJKflip-flopfeaturesindividualJ,K,clock,andasynchronoussetandclearinputsforeachflip-flop.Whentheclockgoeshigh,theinputsar

M74HC112TTR

DUALJ-KFLIPFLOPWITHPRESETANDCLEAR

MC74HC112

DualJ-KFlip-FlopwithSetandReset