General Description

The ICS9179-06 generates low skew clock buffers required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. An output enable is provided for testability.

The device is a buffer with low output to output skew. This is a zero delay buffer device, using an internal PLL. This buffer can be used for phase synchronization to a master clock. With the wide PLL loop BW, this buffer is compatible to Spread Spectrum input clocks from clock generator products such as the ICS9148-27.

特性 Features

? Zero delay buffer, 16 outputs

? Supports up to four SDRAM DIMMS

? Wide PLL loop bandwidth makes this part ideal in Spread Spectrum applications.

? Skew Input to FB_IN –250ps default, with selectable skew -2.7, +2.0, -0.7ns nominal.

? Synchronous clocks skew matched to 250ps window on output.

? 33 to 133MHz input or output frequency.

? I2C Serial Configuration interface to allow individual clocks to be stopped, or selectable delays.

? Multiple VDD, VSS pins for noise reduction

? Slew rate 1.5V/ns into 30pF.

? VDD = 3.3 –5, 0 to 70°C

? All outputs (0:15) tristate with OE low (FB_OUT stays running).

? 48-Pin SSOP package