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I74F74N

Dual D-type flip-flop

DESCRIPTION The74F74isadualpositiveedge-triggeredD-typeflip-flopfeaturingindividualdata,clock,set,andresetinputs;alsotrueandcomplementaryoutputs.Set(SD)andreset(RD)areasynchronousactivelowinputsandoperateindependentlyoftheclockinput.Whensetandresetarein

PHI

I74F74N

Dual D-type flip-flop;

DESCRIPTION\nThe 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output.FEATURE\n? Industrial temperature range available (–40°C to +85°C)

恩XP

N74F74D

DualD-typeflip-flop

DESCRIPTION The74F74isadualpositiveedge-triggeredD-typeflip-flopfeaturingindividualdata,clock,set,andresetinputs;alsotrueandcomplementaryoutputs.Set(SD)andreset(RD)areasynchronousactivelowinputsandoperateindependentlyoftheclockinput.Whensetandresetarein

PHI

N74F74D

DualD-typeflip-flop

FEATURE ?Industrialtemperaturerangeavailable(–40°Cto+85°C) DESCRIPTION The74F74isadualpositiveedge-triggeredD-typeflip-flopfeaturing individualdata,clock,set,andresetinputs;alsotrueand complementaryoutputs.Set(SD)andreset(RD)areasynchronous activelowinputs

N74F74N

DualD-typeflip-flop

DESCRIPTION The74F74isadualpositiveedge-triggeredD-typeflip-flopfeaturingindividualdata,clock,set,andresetinputs;alsotrueandcomplementaryoutputs.Set(SD)andreset(RD)areasynchronousactivelowinputsandoperateindependentlyoftheclockinput.Whensetandresetarein

PHI