I74F109N中文資料飛利浦數(shù)據(jù)手冊PDF規(guī)格書
I74F109N規(guī)格書詳情
DESCRIPTION
The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse.
transition time of the positive-going pulse. The J and K inputs must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. The JK design allows operation as a D flip-flop by tying J and K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation.
FEATURE
? Industrial temperature range available (–40°C to +85°C)
產(chǎn)品屬性
- 型號:
I74F109N
- 功能描述:
觸發(fā)器 I74F109N/DIP16/TUBE-BULK//
- RoHS:
否
- 制造商:
Texas Instruments
- 電路數(shù)量:
2
- 邏輯系列:
SN74
- 邏輯類型:
D-Type Flip-Flop
- 極性:
Inverting, Non-Inverting
- 輸入類型:
CMOS
- 傳播延遲時間:
4.4 ns
- 高電平輸出電流:
- 16 mA
- 低電平輸出電流:
16 mA
- 電源電壓-最大:
5.5 V
- 最大工作溫度:
+ 85 C
- 安裝風(fēng)格:
SMD/SMT
- 封裝/箱體:
X2SON-8
- 封裝:
Reel
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