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HV507PG

300V, 64-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs

GeneralDescription TheHV507isalowvoltageserialtohighvoltageparallelconverterwith64highvoltagepush-pulloutputs.Thisdevicehasbeendesignedforuseasaprinterdriverforelectrostaticapplications.Itcanalsobeusedinanyapplicationrequiringmultiplehighvoltageoutpu

HV507PG-G

64-Channel Serial to Parallel Converter 64-Channel Serial to Parallel Converter

GeneralDescription TheHV507isalowvoltageserialtohighvoltageparallelconverterwith64push-pulloutputs.Thisdevicehasbeendesignedforuseasaprinterdriverforelectrostaticapplications.Itcanalsobeusedinanyapplicationrequiringmultipleoutput,highvoltage,lowcurrent

HV507PG-G

64-Channel Serial to Parallel Converter With High Voltage Push-Pull Outputs; ? Processed with HVCMOS? technology\n? Operating output voltages to 300V\n? Low power level shifting from 5.0 to 300V\n? Shift register speed: 8.0MHz @ VDD = 5.0V\n? 64 latched data outputs\n? Output polarity and blanking\n? CMOS compatible inputs\n? Forward and reverse shifting options;

General Description\nThe HV507 is a low voltage serial to high voltage parallel converter with 64 push-pull outputs. This device has been designed for use as a printer driver for electrostatic applications. It can also be used in any application requiring multiple output, high voltage, low current sourcing and sinking capabilities.\nThe device consists of a 64-bit shift register, 64 latches, and control logic to perform the polarity select and blanking of the outputs. A DIR pin controls the direction of data shift through the device. With DIR grounded, DIOA is Data-In and DIOB is Data-Out; data is shifted from HVOUT64 to HVOUT1. When DIR is at logic high, DIOB is Data-In and DIOA is Data-Out: data is then shifted from HV OUT1 to HVOUT64. Data is shifted through the shift register on the low to high transition of the clock. Data output buffers are provided for cascading devices. Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL(polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE is high. The data in the latch is stored during LE transition from high to low.

HV507PG-G

Package：80-BQFP；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：串行至并行 類別：集成電路（IC） 移位寄存器 描述：IC 64BIT SRL PARALLEL 325V 80QFP

HV507X

300V,64-ChannelSerialtoParallelConverterwithHighVoltagePush-PullOutputs

GeneralDescription TheHV507isalowvoltageserialtohighvoltageparallelconverterwith64highvoltagepush-pulloutputs.Thisdevicehasbeendesignedforuseasaprinterdriverforelectrostaticapplications.Itcanalsobeusedinanyapplicationrequiringmultiplehighvoltageoutpu

I507ERW

Ultra-Miniature5WSingle&DualOutputDC/DCConverters

I507RU

4:1Input,5WUltra-MiniatureDC/DCConverters

ICS507-XX

PECLClockSynthesizer

Description TheICS507-01andICS507-02areinexpensivewaystogeneratealowjitter155.52MHz(orotherhighspeed)differentialPECLclockoutputfromalowfrequencycrystalinput.UsingPhase-Locked-Loop(PLL)techniques,thedevicesuseastandardfundamentalmodecrystaltoproduceout

J507

CURRENTREGULATINGDIODES

FEATURES SECONDSOURCEFORSILICONIXJ500SERIES WIDECURRENTRANGE0.192to5.6mA BIASINGNOTREQUIREDVGS=0V

J507

CurrentRegulatorDiodes

DESCRIPTION TheJ500seriesisafamilyof±20rangecurrentregulatorsdesignedfordemandingapplicationsintestequipmentandinstrumentation.ThesedevicesutilizetheJFETtechniquestoproduceasingletwo-leadeddevicewhichisextremelysimpletooperate. FEATURES ●Two-LeadPlasticP