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HEF4040BT

12-stage binary ripple counter; ? Tolerant of slow clock rise and fall time\n? Fully static operation\n? 5 V, 10 V, and 15 V parametric ratings\n? Standardized symmetrical output characteristics\n? Specified from -40 °C to +85 °C\n? Complies with JEDEC standard JESD 13-B\n;

The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its Schmitt trigger action.\n It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS(usually ground). Unused inputs must be connected to VDD, VSS, or another input.\n

HEF4040BT-Q100

12-stage binary ripple counter; ? Automotive product qualification in accordance with AEC-Q100 (Grade 3)? Specified from -40 °C to +85 °C\n\n? Tolerant of slow clock rise and fall time\n? Fully static operation\n? 5 V, 10 V and 15 V parametric ratings\n? Standardized symmetrical output characteristics\n? ESD protection:? MIL-STD-883, method 3015 exceeds 2000 V\n? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)\n\n? Complies with JEDEC standard JESD 13-B\n;

The HEF4040B-Q100 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its Schmitt trigger action.\n It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications.\n

HEF4040BT-Q100

12-stage binary ripple counter

1.Generaldescription TheHEF4040Bisa12-stagebinaryripplecounterwithaclockinput(CP),anoverriding asynchronousmasterresetinput(MR)andtwelvefullybufferedoutputs(Q0toQ11).Thecounter advancesontheHIGH-to-LOWtransitionofCP.AHIGHonMRclearsallcounterstagesand

HEF4040B-Q100

12-stage binary ripple counter

HEF4040BT-Q100

12-stage binary ripple counter

HEF4040BT,652

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：管件 類別：集成電路（IC） 計數(shù)器，除法器 描述：IC COUNTER RIP BIN 12BIT 16-SOIC

ETC

HEF4040BT,653

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：管件 類別：集成電路（IC） 計數(shù)器，除法器 描述：IC COUNTER BINARY 12STAGE 16SOIC

ETC

HEF4040BT-Q100J

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：管件 類別：集成電路（IC） 計數(shù)器，除法器 描述：IC RIPPLE COUNTER 12ST 16SOIC

ETC