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首頁>HEF4029BP>規(guī)格書詳情

HEF4029BP中文資料飛利浦數(shù)據(jù)手冊PDF規(guī)格書

HEF4029BP
廠商型號

HEF4029BP

功能描述

Synchronous up/down counter, binary/decade counter

文件大小

188.66 Kbytes

頁面數(shù)量

14

生產(chǎn)廠商

PHI

中文名稱

飛利浦

數(shù)據(jù)手冊

下載地址一下載地址二

更新時間

2025-8-10 10:19:00

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HEF4029BP價格和庫存,歡迎聯(lián)系客服免費人工找貨

HEF4029BP規(guī)格書詳情

DESCRIPTION

The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input (PL), four parallel data inputs (P0 to P3), four parallel buffered outputs (O0 to O3) and an active LOW terminal count output (TC).

Information on P0 to P3 is asynchronously loaded into the counter while PL is HIGH, independent of CP.

The counter is advanced one count on the LOW to HIGH transition of CP when CE and PL are LOW. The TC signal is normally HIGH and goes LOW when the counter reaches its maximum count in the UP mode, or the minimum count in the DOWN mode provided CE is LOW.

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43200
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100
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PHI
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PHI
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ST
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25+
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54648
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23+
3.9MM
7300
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ATTEN
23+
DIP
71596
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