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HEF4021BT

8-bit static shift register

DESCRIPTION TheHEF4021Bisan8-bitstaticshiftregister(parallel-to-serialconverter)withasynchronousserialdatainput(DS),aclockinput(CP),anasynchronousactiveHIGHparallelloadinput(PL),eightasynchronousparalleldatainputs(P0toP7)andbufferedparalleloutputsfromth

HEF4021BT

8-bit static shift register

1.Generaldescription TheHEF4021Bisan8-bitstaticshiftregister(parallel-to-serialconverter)withasynchronous serialdatainput(DS),aclockinput(CP),anasynchronousactiveHIGHparallelloadinput(PL), eightasynchronousparalleldatainputs(D0toD7)andbufferedparalleloutp

HEF4021BT

8-bit static shift register; ? Tolerant of slower rise and fall times\n? Fully static operation\n? 5 V, 10 V, and 15 V parametric ratings\n? Standardized symmetrical output characteristics\n? Specified from -40 °C to +125 °C\n? Complies with JEDEC standard JESD 13-B\n;

The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7).\n Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.\n It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.\n

HEF4021BTT

8-bit static shift register

1.Generaldescription TheHEF4021Bisan8-bitstaticshiftregister(parallel-to-serialconverter)withasynchronous serialdatainput(DS),aclockinput(CP),anasynchronousactiveHIGHparallelloadinput(PL), eightasynchronousparalleldatainputs(D0toD7)andbufferedparalleloutp

HEF4021BTT

8-bit static shift register; ? Tolerant of slower rise and fall times\n? Fully static operation\n? 5 V, 10 V, and 15 V parametric ratings\n? Standardized symmetrical output characteristics\n? Specified from -40 °C to +125 °C\n? Complies with JEDEC standard JESD 13-B\n;

The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7).\n Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.\n It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.\n

HEF4021BTT-Q100

8-bit static shift register; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n? Tolerant of slower rise and fall times\n? Fully static operation\n? 5 V, 10 V, and 15 V parametric ratings\n? Standardized symmetrical output characteristics\n? ESD protection:? MIL-STD-833, method 3015 exceeds 2000 V\n? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)\n\n? Complies with JEDEC standard JESD 13-B\n;

The HEF4021B-Q100 is an 8-bit static shift register (parallel-to-serial converter). It has a synchronous serial data input (DS), a clock input (CP) and an asynchronous active HIGH parallel load input (PL). The HEF4021B-Q100 also has eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position. All the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Connect unused inputs must to VDD, VSS, or another input.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

HEF4021BT-Q100

8-bit static shift register

HEF4021BTT-Q100

8-bit static shift register

HEF4021BT,653

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：并行或串行至串行 類別：集成電路（IC） 移位寄存器 描述：IC STATIC SHIFT REG 8BIT 16SOIC

Nexperia USA Inc.

HEF4021BT-Q100J

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR） 功能：并行或串行至串行 類別：集成電路（IC） 移位寄存器 描述：IC SHIFT REGISTER 8BIT 16SOIC

Nexperia USA Inc.