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HEF40175BT

Quadruple D-type flip-flop

DESCRIPTION TheHEF40175Bisaquadrupleedge-triggeredD-typeflip-flopwithfourdatainputs(D0toD3),aclockinput(CP),anoverridingasynchronousmasterresetinput(MR),fourbufferedoutputs(O0toO3),andfourcomplementarybufferedoutputs(O0toO3).InformationonD0toD3istrans

HEF40175BT

Quad D-type flip-flop

1.Generaldescription TheHEF40175BisaquadpositiveedgetriggeredD-typeflip-flopwithfourdata(Dn)inputs, commonclock(CP)andasynchronousmasterreset(MR)inputs,andcomplementaryQnandQn outputs.WhenMRisHIGHdataattheD-inputthatmeetstheset-upandholdtimerequireme

HEF40175BT

Quad D-type flip-flop; ? Fully static operation\n? 5 V, 10 V, and 15 V parametric ratings\n? Standardized symmetrical output characteristics\n? Specified from –40 ℃ to +125 ℃\n? Complies with JEDEC standard JESD 13-B\n;

The HEF40175B is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (Q0 to Q3), and four complementary buffered outputs (Q0 to Q3). Information on D0 to D3 is transferred to Q0 to Q3 on the LOW-to-HIGH transition of CP if MR is HIGH. When LOW, MR resets all flip-flops (Q0 to Q3 = LOW; Q0 to Q3 = HIGH), independent of CP and D0 to D3.\n It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.\n

HEF40175BTT

Quad D-type flip-flop

1.Generaldescription TheHEF40175BisaquadpositiveedgetriggeredD-typeflip-flopwithfourdata(Dn)inputs, commonclock(CP)andasynchronousmasterreset(MR)inputs,andcomplementaryQnandQn outputs.WhenMRisHIGHdataattheD-inputthatmeetstheset-upandholdtimerequireme

HEF40175BTT

Quad D-type flip-flop; ? Fully static operation\n? 5 V, 10 V, and 15 V parametric ratings\n? Standardized symmetrical output characteristics\n? Specified from –40 ℃ to +125 ℃\n? Complies with JEDEC standard JESD 13-B\n;

The HEF40175B is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (Q0 to Q3), and four complementary buffered outputs (Q0 to Q3). Information on D0 to D3 is transferred to Q0 to Q3 on the LOW-to-HIGH transition of CP if MR is HIGH. When LOW, MR resets all flip-flops (Q0 to Q3 = LOW; Q0 to Q3 = HIGH), independent of CP and D0 to D3.\n It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.\n

HEF40175BTT-Q100

Quad D-type flip-flop; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n? Wide supply voltage range from 3.0 V to 15.0 V\n? CMOS low power dissipation\n? High noise immunity\n? Fully static operation\n? 5 V, 10 V, and 15 V parametric ratings\n? Standardized symmetrical output characteristics\n? Complies with JEDEC standard JESD 13-B\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-B exceeds 200 V\n;

The HEF40175B-Q100 is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn and Qn outputs. When MR is HIGH data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. When LOW, MR resets all flip-flops (Qn = LOW, Qn = HIGH), independent of CP and Dn. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

HEF40175BT,652

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：管件 功能：主復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 4BIT 16SO

Nexperia USA Inc.

HEF40175BT,653

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：主復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 4BIT 16SO

Nexperia USA Inc.

HEF40175BTT,118

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：主復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 4BIT 16TSSOP

Nexperia USA Inc.