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HEF4015BP

Dual 4-bit static shift register;

General description\nThe HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (MR). Information present on D is shifted to the first register position, and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. A HIGH on MR clears the register and forces Q0 to Q3 to LOW, independent of CP and D. The clock input’s Schmitt trigger action makes the input highly tolerant of slower clock rise and fall times.\nIt operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.Features and benefits\n■ Tolerant of slow clock rise and fall times\n■ Fully static operation\n■ 5 V, 10 V, and 15 V parametric ratings\n■ Standardized symmetrical output characteristics\n■ Specified from -40 °C to +85 °C.\n■ Complies with JEDEC standard JESD 13-B

恩XP

HEF4015BP

Dual 4-bit static shift register

DESCRIPTION TheHEF4015Bisadualedge-triggered4-bitstaticshiftregister(serial-to-parallelconverter).Eachshiftregisterhasaserialdatainput(D),aclockinput(CP),fourfullybufferedparalleloutputs(O0toO3)andanoverridingasynchronousmasterresetinput(MR).Informationpr

PHI

HEF4015BP

Tolerant of slow clock rise and fall times

ETC

HEF4015BT

Dual4-bitstaticshiftregister

DESCRIPTION TheHEF4015Bisadualedge-triggered4-bitstaticshiftregister(serial-to-parallelconverter).Eachshiftregisterhasaserialdatainput(D),aclockinput(CP),fourfullybufferedparalleloutputs(O0toO3)andanoverridingasynchronousmasterresetinput(MR).Informationpr

PHI

HEF4015BT

Dual4-bitstaticshiftregister

1.Generaldescription TheHEF4015Bisadualedge-triggered4-bitstaticshiftregister(serial-to-parallelconverter).Each shiftregisterhasaserialdatainput(nD),aclockinput(nCP),fourfullybufferedparalleloutputs (Q0toQ3)andanoverridingasynchronousmasterresetinput(nMR)