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首頁(yè)>HD74HCT563>規(guī)格書(shū)詳情

HD74HCT563中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

HD74HCT563
廠商型號(hào)

HD74HCT563

功能描述

Octal Transparent Latches (with 3-state outputs)

文件大小

138.1 Kbytes

頁(yè)面數(shù)量

10 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
RENESAS
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-1 16:59:00

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HD74HCT563規(guī)格書(shū)詳情

描述 Description

When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D inputs and the Q outputs of HD74HCT573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.

特性 Features

? LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility

? High Speed Operation: tpd (Data to Q, Q) = 13 ns typ (CL = 50 pF)

? High Output Current: Fanout of 15 LSTTL Loads

? Wide Operating Voltage: VCC = 4.5 to 5.5 V

? Low Input Current: 1 μA max

? Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C)

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