描述 Description

This circuit contains eight master-slave flip-flops and additional gating to implement two individual 4-bit decade counters. Each decade counter has individual clock, clear and set-to-9 inputs. BCD count sequences of any length up to divide-by-100 may be implemented with a single HD74HC490. Buffering on each output is provided to ensure that suceptibility to collector communication is reduced significantly. The counters have paralle outputs from each counter state so that submultiples of the input count frequency are available for system timing signals.

特性 Features

? High Speed Operation: tpd (Clock to QA) = 13 ns typ (CL = 50 pF)

? High Output Current: Fanout of 10 LSTTL Loads

? Wide Operating Voltage: VCC = 2 to 6 V

? Low Input Current: 1 μA max

? Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C)