描述 Description

Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and changes state on the positive going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic level on the corresponding input.

特性 Features

? High Speed Operation: tpd(Clock to Q) = 15 ns typ (CL= 50 pF)

? High Output Current: Fanout of 10 LSTTL Loads

? Wide Operating Voltage: VCC= 2 to 6 V

? Low Input Current: 1 μA max

? Low Quiescent Supply Current: ICC(static) = 2 μA max (Ta = 25°C)