HCF40103B屬于集成電路（IC）的計數(shù)器除法器。由意法半導體集團制造生產(chǎn)的HCF40103B計數(shù)器，除法器計數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對輸入發(fā)生的邏輯轉換進行計數(shù)，然后使用多個并行輸出重新發(fā)送累加的計數(shù)，和/或生成單個輸出信號轉換，從而對應用某些整數(shù)數(shù)量輸入信號轉換進行響應。除了簡單的事件計數(shù)，它們還可用于各種頻率合成應用。

DESCRIPTION

The HCC40102B, HCC40103B, (extended temperature range) and the HCF40102B, HCF40103B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package. The HCC/HCF40102B, and HCC/HCF40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The HCC/HCF40102B is configured as two cascaded 4-bit BCD counters, and the HCC/HCF40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously.

40102B 2-DECADE BCD TYPE

40103B 8-BIT BINARY TYPE

■ SYNCHRONOUS OR ASYNCHRONOUS PRESET

■ MEDIUM-SPEED OPERATION : fCL = 3.6MHz (TYP.) @ VDD = 10V

■ CASCADABLE

■ QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE

■ 5V, 10V AND 15V PARAMETRIC RATINGS

■ INPUT CURRENT OF100 nA AT 18V AND 25°C FOR HCC DEVICE

■ 100 TESTED FOR QUIESCENT CURRENT

■ MEETS ALL REQUIREMENTS OF JEDECTENTATIVE

STANDARD No. 13 A, ”STANDARD

SPECIFICATIONS FOR DESCRIPTION OF ”B”

SERIES CMOS DEVICES”