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CD74HC75M96.A

Marking：HC75M；Package：SOIC；Dual 2-Bit Bistable Transparent Latch

Features ?TrueandComplementaryOutputs ?BufferedInputsandOutputs ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?WideOperatingTemperatureRange...-55oCto125oC ?B

CD74HC75MT

Marking：HC75M；Package：SOIC；Dual 2-Bit Bistable Transparent Latch

Features ?TrueandComplementaryOutputs ?BufferedInputsandOutputs ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?WideOperatingTemperatureRange...-55oCto125oC ?B

CD74HCT03M

Marking：HCT03M；Package：SOIC；High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain

Features ?BufferedInputs ?TypicalPropagationDelay:8nsatVCC=5V, CL=15pF,TA=25oC ?OutputPull-upto10V ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?WideOpera

CD74HCT03M96

Marking：HCT03M；Package：SOIC；High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain

Features ?BufferedInputs ?TypicalPropagationDelay:8nsatVCC=5V, CL=15pF,TA=25oC ?OutputPull-upto10V ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?WideOpera

CD74HCT03M96.A

Marking：HCT03M；Package：SOIC；High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain

Features ?BufferedInputs ?TypicalPropagationDelay:8nsatVCC=5V, CL=15pF,TA=25oC ?OutputPull-upto10V ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?WideOpera

CD74HCT109M

Marking：HCT109M；Package：SOIC；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features ?AsynchronousSetandReset ?SchmittTriggerClockInputs ?TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?Wi

CD74HCT109M96

Marking：HCT109M；Package：SOIC；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features ?AsynchronousSetandReset ?SchmittTriggerClockInputs ?TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?Wi

CD74HCT109M96.A

Marking：HCT109M；Package：SOIC；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features ?AsynchronousSetandReset ?SchmittTriggerClockInputs ?TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?Wi

CD74HCT123M96.A

Marking：HCT123M；Package：SOIC；High-Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets

Features ?OverridingResetTerminatesOutputPulse ?TriggeringFromtheLeadingorTrailingEdge ?QandQBufferedOutputs ?SeparateResets ?WideRangeofOutput-PulseWidths ?SchmittTriggeronBothAandBInputs ?Fanout(OverTemperatureRange) -StandardOutputs........

CD74HCT137M96

Marking：HCT137M；Package：SOIC；High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Features ?SelectOneofEightDataOutputs -ActiveLowforCD74HC137andCD74HCT137 -ActiveHighfor’HC237andCD74HCT237 ?l/OPortorMemorySelector ?TwoEnableInputstoSimplifyCascading ?TypicalPropagationDelayof13nsatVCC=5V, 15pF,TA=25oC(CD74HC237) ?Fanout(Over