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首頁(yè)>H5AN4G4NAFR-PBC>規(guī)格書詳情

H5AN4G4NAFR-PBC中文資料海力士數(shù)據(jù)手冊(cè)PDF規(guī)格書

H5AN4G4NAFR-PBC
廠商型號(hào)

H5AN4G4NAFR-PBC

功能描述

4Gb DDR4 SDRAM Lead-Free&Halogen-Free (RoHS Compliant)

文件大小

725.21 Kbytes

頁(yè)面數(shù)量

45 頁(yè)

生產(chǎn)廠商

HYNIX

中文名稱

海力士

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-10 10:02:00

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H5AN4G4NAFR-PBC規(guī)格書詳情

描述 Description

The H5AN4G4NAFR-xxC, H5AN4G8NAFR-xxC and H5AN4G6NAFR-xxC are a 4Gb CMOS Double Data Rate

IV (DDR4) Synchronous DRAM, ideally suited for the main memory applications which requires large memory

density and high bandwidth. SK hynix 4Gb DDR4 SDRAMs offer fully synchronous operations referenced

to both rising and falling edges of the clock. While all addresses and control inputs are latched on

the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are

sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

FEATURES

? VDD=VDDQ=1.2V +/- 0.06V

? Fully differential clock inputs (CK, CK) operation

? Differential Data Strobe (DQS, DQS) ? On chip DLL align DQ, DQS and DQS transition with CK ? transition

? DM masks write data-in at the both rising and falling ? edges of the data strobe

? All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock

? Programmable CAS latency 9, 11, 12, 13, 14, 15, 16, 17, 18, 19 and 20

? Programmable additive latency 0, CL-1, and CL-2 ? supported (x4/x8 only)

? Programmable CAS Write latency (CWL) = 9, 10, 11, 12, 14, 16, 18

? Programmable burst length 4/8 with both nibble ? sequential and interleave mode

? BL switch on the fly

? 16banks

? Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 μs at 0oC ~ 85 oC - 3.9 μs at 85oC ~ 95 oC

? JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16)

? Driver strength selected by MRS

? Dynamic On Die Termination supported

? Two Termination States such as RTT_PARK and RTT_NOM switchable by ODT pin

? Asynchronous RESET pin supported

? ZQ calibration supported

? TDQS (Termination Data Strobe) supported (x8 only)

? Write Levelization supported

? 8 bit pre-fetch

? This product in compliance with the RoHS directive.

? Internal Vref DQ level generation is available

? Write CRC is supported at all speed grades

? Maximum Power Saving Mode is supported

? TCAR(Temperature Controlled Auto Refresh) mode is supported

? LP ASR(Low Power Auto Self Refresh) mode is sup-ported

? Fine Granularity Refresh is supported

? Per DRAM Addressability is supported

? Geardown Mode(1/2 rate, 1/4 rate) is supported

? Programable Preamble for read and write is supported

? Self Refresh Abort is supported

? CA parity (Command/Address Parity) mode is sup-ported

? Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or differentbank group accesses are available

? DBI(Data Bus Inversion) is supported(x8)

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
SKHYNIX
19+
FBGA
2000
正規(guī)渠道原裝正品
詢價(jià)
SKHYNIX
20+
FBGA-96
3525
原裝正品現(xiàn)貨
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HYNIX
23+
BGA
50000
全新原裝正品現(xiàn)貨,支持訂貨
詢價(jià)
SKHYNIX
24+
BGA
20000
全新原廠原裝,進(jìn)口正品現(xiàn)貨,正規(guī)渠道可含稅??!
詢價(jià)
SKHYNIX
23+
BGA
6500
專注配單,只做原裝進(jìn)口現(xiàn)貨
詢價(jià)
SKHYNIX
23+
BGA
3000
一級(jí)代理原廠VIP渠道,專注軍工、汽車、醫(yī)療、工業(yè)、
詢價(jià)
SKHYINX
17+
BGA
3807
原裝現(xiàn)貨
詢價(jià)
SKHYNIX
23+
FBGA
18204
原裝正品代理渠道價(jià)格優(yōu)勢(shì)
詢價(jià)
SKhynic
16+
FBGA96
6200
原裝正品現(xiàn)貨,可開發(fā)票,假一賠十
詢價(jià)
SKHYNIX
20+
BGA
19570
原裝優(yōu)勢(shì)主營(yíng)型號(hào)-可開原型號(hào)增稅票
詢價(jià)