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GTLP10B320

10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path

GeneralDescription TheGTLP10B320isa10-bitUniversalbusdriverandreceiver,withseparateLVTTLinputsandoutputsandafeedbackpathfordiagnostics,thatprovidesLVTTLtoGTLPsignalleveltranslation.HighspeedbackplaneoperationisadirectresultofGTLP’sreducedoutputswing( F

GTLP10B320MTD

10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path

GeneralDescription TheGTLP10B320isa10-bitUniversalbusdriverandreceiver,withseparateLVTTLinputsandoutputsandafeedbackpathfordiagnostics,thatprovidesLVTTLtoGTLPsignalleveltranslation.HighspeedbackplaneoperationisadirectresultofGTLP’sreducedoutputswing( F

GTLP10B320MTD

10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path; ■ Bidirectional interface between GTLP and LVTTL logic levels\n■ Variable edge rate control pin to select desired edge rate on GTLP port (VERC)\n■ VREF pin provides external supply reference voltage for receiver threshold adjustibility\n■ Split LVTTL inputs and outputs\n■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature\n■ A feedback path for control and diagnostics monitoring\n■ TTL compatible driver and control inputs\n■ Designed using Fairchild advanced BiCMOS technology\n■ Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs\n■ Power up/down and power off high impedance for liveinsertion\n■ Open drain on GTLP to support wired-or connection\n■ Flow through pinout optimizes PCB layout\n■ A Port source/sink ?24mA/+24mA\n■ B Port sink +50mA;

General Description\nThe GTLP10B320 is a 10-bit Universal bus driver and receiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL to GTLP signal level translation. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.

GTLP10B320MTD

Package：56-TFSOP（0.240"，6.10mm 寬）；包裝：管件 類別：集成電路（IC） 通用總線功能 描述：IC UNIV BUS DVR 10BIT 56TSSOP

GTLP10B320MTDX

Package：56-TFSOP（0.240"，6.10mm 寬）；包裝：管件 類別：集成電路（IC） 通用總線功能 描述：IC UNIV BUS DVR 10BIT 56TSSOP