GS9091B屬于集成電路（IC）的視頻處理。由升特制造生產(chǎn)的GS9091B視頻處理一種集成電路 (IC) 半導(dǎo)體器件，設(shè)計(jì)用于在放大、增強(qiáng)、編碼器和解碼器（編解碼器）、緩沖、校準(zhǔn)、處理、信號(hào)調(diào)節(jié)、調(diào)制與解調(diào)、轉(zhuǎn)換、傳輸、伽瑪校正、切換、OSD、數(shù)字化和多路復(fù)用等應(yīng)用中處理音頻和/或視頻信號(hào)。

描述 Description

The GS9091B is a 270Mb/s equalizing and reclocking dese rializer with an internal FIFO. It provides a complete receive solution for SD-SDI and DVB-ASI applications.

In addition to equalizing, reclocking and deserializing the input data stream, the GS9091B performs NRZI -to-NRZ decoding, descrambling as per SMPTE 259M-C, and word alignment when operating in SMPTE mode. When operating in DVB-ASI mode, the device will word align the data to K28.5 sync characters and 8b/10b decode the received stream.

The integrated equalizer is optimized for 270Mb/s and can typically equalize up to 500m of Belden 1694A cable. Both the equalizer and the internal reclocker are fully compatible with both SMPTE and DVB-ASI input streams.

The GS9091B includes a range of data processing functions such as EDH support (error detection and handling), and automatic standards detection. The device can also detect and extract SMPTE 352M payload identifier packets and in dependently identify the received video standard. This in formation is read from internal registers via the host interface port.

The GS9091B also incorporates a video line-based FIFO.

This FIFO may be used in four user-selectable modes to carry out tasks such as data alignment / delay, clock phase interchange, MPEG packet extraction and clock rate interchange, and ancillary data packet extraction.

Parallel data outputs are provided in 10-bit multiplexed format, with the associated parallel clock output signal operating at 27MHz.

The device may also be used in a low-latency data pass through mode where only descrambling and word alignment will be performed in SMPTE mode.

Key Features

? SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding (with bypass)

? DVB-ASI 8b/10b decoding

? Integrated Cable Equalizer

? 500m typical equalization of Belden 1694A cable

? Integrated line-based FIFO for data alignment/delay, clock phase interchange, DVB-ASI data packet extraction and clock rate interchange, and ancillary data packet extraction

? Integrated VCO and reclocker

? User selectable additional processing features including:

? TRS, ANC data checksum, and EDH CRC error detection and correction

? programmable ANC data detection

? illegal code remapping

? Internal flywheel for noise immune H, V, F extraction

? Automatic standards detection and indication

? Enhanced Gennum Serial Peripheral Interface (GSPI)

? JTAG test interface

? Polarity insensitive for DVB-ASI and SMPTE signals

? +1.8V core power supply with optional +1.8V or +3.3V I/O power supply

? Small footprint (11mm x 11mm)

? Low power operation (typically 350mW)

? Pb-free and RoHS compliant

Applications

? SMPTE 259M-C Serial Digital Interfaces

? DVB-ASI Serial Digital Interfaces