[GSI]

Functional Description

The GS882Z818/36B is an 8Mbit Synchronous Static SRAM. GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

特性 Features

? 512K x 18 and 256K x 36 configurations

? User-configurable Pipelined and Flow Through mode

? NBT (No Bus Turn Around) functionality allows zero wait

? Read-Write-Read bus utilization

? Fully pin-compatible with both pipelined and flow through NtRAM?, NoBL? and ZBT? SRAMs

? IEEE 1149.1 JTAG-compatible Boundary Scan

? On-chip write parity checking; even or odd selectable

? ZQ mode pin for user selectable high/low output drive strength.

? x16/x32 mode with on-chip parity encoding and error detection

? Pin-compatible with 2M, 4M and 16M devices

? 3.3 V +10/–5 core power supply

? 2.5 V or 3.3 V I/O supply

? LBO pin for Linear or Interleave Burst mode

? Byte write operation (9-bit Bytes)

? 3 chip enable signals for easy depth expansion

? Clock Control, registered, address, data, and control

? ZZ Pin for automatic power-down

? JEDEC-standard 119-Bump BGA package