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EPM7064STC44-10

Programmable Logic Device Family

GeneralDescription TheMAX7000familyofhigh-density,high-performancePLDsisbasedonAltera’ssecond-generationMAXarchitecture.FabricatedwithadvancedCMOStechnology,theEEPROM-basedMAX7000familyprovides600to5,000usablegates,ISP,pin-to-pindelaysasfastas5ns,andcounte

EPM7064STC44-10

Package：44-TQFP；包裝：托盤 類別：集成電路（IC） CPLD（復雜可編程邏輯器件） 描述：IC CPLD 64MC 10NS 44TQFP

EPM7064STC44-10N

EPM7064STC44-10N - 芯片, 可編程邏輯器件 MAX ISP PLD; ·Built-in JTAG boundary-scan test\n·PCI-compliant devices available\n·5ns pin-to-pin logic delays with up to 175.4MHz counter frequencies\n·Open-drain output option\n·Programmable macrocell flip-flops with individual clear, preset, clock and clock enable controls\n·Programmable power-saving mode for a reduction of over 50% in each macrocell\n·Six pin or logic-driven output enable signals\n·Two global clock signals with optional inversion\n·Enhanced interconnect resources for improved routability\n·Programmable output slew-rate control\n;

The EPM7064STC44-10N is a high-density, high-performance Programmable Logic Device (PLD) based on second-generation MAX? architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5000 usable gates, ISP, pin-to-pin delays as fast as 5ns and counter speeds of up to 175.4MHz. Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys and VeriBest.

EPM7064STC44-10FN

Package：44-TQFP；包裝：托盤 類別：集成電路（IC） CPLD（復雜可編程邏輯器件） 描述：IC CPLD 64MC 10NS 44TQFP

EPM7064STC44-10N

Package：44-TQFP；包裝：托盤 類別：集成電路（IC） CPLD（復雜可編程邏輯器件） 描述：IC CPLD 64MC 10NS 44TQFP