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首頁(yè)>EPM7064AELI44-7N>規(guī)格書(shū)詳情

EPM7064AELI44-7N中文資料阿爾特?cái)?shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

EPM7064AELI44-7N
廠商型號(hào)

EPM7064AELI44-7N

功能描述

Programmable Logic Device

文件大小

1.01845 Mbytes

頁(yè)面數(shù)量

64 頁(yè)

生產(chǎn)廠商

ALTERA

中文名稱

阿爾特

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-7 20:00:00

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EPM7064AELI44-7N規(guī)格書(shū)詳情

General Description

MAX 7000A (including MAX 7000AE) devices are high-density, high-performance devices based on Altera’s second-generation MAX architecture.

Features...

■ High-performance 3.3-V EEPROM-based programmable logic

devices (PLDs) built on second-generation Multiple Array MatriX

(MAX?) architecture (see Table 1)

■ 3.3-V in-system programmability (ISP) through the built-in

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with

advanced pin-locking capability

– MAX 7000AE device in-system programmability (ISP) circuitry

compliant with IEEE Std. 1532

– EPM7128A and EPM7256A device ISP circuitry compatible with

IEEE Std. 1532

■ Built-in boundary-scan test (BST) circuitry compliant with

IEEE Std. 1149.1

■ Supports JEDEC Jam Standard Test and Programming Language

(STAPL) JESD-71

■ Enhanced ISP features

– Enhanced ISP algorithm for faster programming (excluding

EPM7128A and EPM7256A devices)

– ISP_Done bit to ensure complete programming (excluding

EPM7128A and EPM7256A devices)

– Pull-up resistor on I/O pins during in-system programming

■ Pin-compatible with the popular 5.0-V MAX 7000S devices

■ High-density PLDs ranging from 600 to 10,000 usable gates

■ Extended temperature range

■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to

227.3 MHz

■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while

I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels

■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack

(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space

saving FineLine BGATM, and plastic J-lead chip carrier (PLCC)

packages

■ Supports hot-socketing in MAX 7000AE devices

■ Programmable interconnect array (PIA) continuous routing structure

for fast, predictable performance

■ PCI-compatible

■ Bus-friendly architecture, including programmable slew-rate control

■ Open-drain output option

■ Programmable macrocell registers with individual clear, preset,

clock, and clock enable controls

■ Programmable power-up states for macrocell registers in

MAX 7000AE devices

■ Programmable power-saving mode for 50 or greater power

reduction in each macrocell

■ Configurable expander product-term distribution, allowing up to

32 product terms per macrocell

■ Programmable security bit for protection of proprietary designs

■ 6 to 10 pin- or logic-driven output enable signals

■ Two global clock signals with optional inversion

■ Enhanced interconnect resources for improved routability

■ Fast input setup times provided by a dedicated path from I/O pin to

macrocell registers

■ Programmable output slew-rate control

■ Programmable ground pins

產(chǎn)品屬性

  • 型號(hào):

    EPM7064AELI44-7N

  • 功能描述:

    CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 36 IOs

  • RoHS:

  • 制造商:

    Lattice

  • 存儲(chǔ)類型:

    EEPROM

  • 大電池?cái)?shù)量:

    128

  • 最大工作頻率:

    333 MHz

  • 延遲時(shí)間:

    2.7 ns

  • 可編程輸入/輸出端數(shù)量:

    64

  • 工作電源電壓:

    3.3 V

  • 最大工作溫度:

    + 90 C

  • 最小工作溫度:

    0 C

  • 封裝/箱體:

    TQFP-100

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
ALTERA
25+
PLCC-44
90
原裝正品,假一罰十!
詢價(jià)
ALTERA
20+
PLCC44
19570
原裝優(yōu)勢(shì)主營(yíng)型號(hào)-可開(kāi)原型號(hào)增稅票
詢價(jià)
Intel / Altera
24+
PLCC-44
5000
全新原廠原裝,進(jìn)口正品現(xiàn)貨,正規(guī)渠道可含稅!!
詢價(jià)
ALTERA
2016+
PLCC
6528
只做進(jìn)口原裝現(xiàn)貨!或者訂貨,假一賠十!
詢價(jià)
ALTERA
1013
PLC
100
一級(jí)代理,專注軍工、汽車(chē)、醫(yī)療、工業(yè)、新能源、電力
詢價(jià)
22+
5000
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ALTERA
23+
132
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ALTERA
21+
PLC
687
原裝現(xiàn)貨假一賠十
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ALTERA
24+
PLCC-44
8762
公司原廠原裝現(xiàn)貨假一罰十!特價(jià)出售!強(qiáng)勢(shì)庫(kù)存!
詢價(jià)
ALT
2018+
QFP
26976
代理原裝現(xiàn)貨/特價(jià)熱賣(mài)!
詢價(jià)