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EPM3032ALC44-10

Programmable Logic Device Family

GeneralDescription MAX3000Adevicesarelow–cost,high–performancedevicesbasedontheAlteraMAXarchitecture. Features... ■High–performance,low–costCMOSEEPROM–basedprogrammable logicdevices(PLDs)builtonaMAX?architecture(seeTable1) ■3.3-Vin-systemprogrammabilit

EPM3032ALC44-10

Programmable logic , 32 macrocells, 2 logic array blocks, 34 I/O pins, 10ns;

Features...■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX architecture\n■ 3.3-V in-system programmability(ISP) through the built–in IEEE Std. 1149.1 Joint Test ActionGroup (JTAG) interface with advanced pin-locking capability\n– ISP circuitry compliant with IEEE Std. 1532\n■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990\n■ Enhanced ISP features:\n– Enhanced ISP algorithm for faster programming\n– ISP_Done bit to ensure complete programming\n– Pull-up resistor on I/O pinsduring in–system programming\n■ High–density PLDs ranging from 600 to 10,000 usable gates\n■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz\n■ MultiVolt I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels

EPM3032ALC44-10

Programmable Logic Device Family

EPM3032ALC44-10

Package：44-LCC（J 形引線）；包裝：管件 類別：集成電路（IC） CPLD（復雜可編程邏輯器件） 描述：IC CPLD 32MC 10NS 44PLCC

EPM3032ALC44-10N

Programmable Logic Device Family

GeneralDescription MAX3000Adevicesarelow–cost,high–performancedevicesbasedontheAlteraMAXarchitecture. Features... ■High–performance,low–costCMOSEEPROM–basedprogrammable logicdevices(PLDs)builtonaMAX?architecture(seeTable1) ■3.3-Vin-systemprogrammabilit

EPM3032ALC44-10N

Programmable Logic Device Family

EPM3032ALC44-10N

Package：44-LCC（J 形引線）；包裝：托盤 類別：集成電路（IC） CPLD（復雜可編程邏輯器件） 描述：IC CPLD 32MC 10NS 44PLCC