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EP1C3T100C8N

EP1C3T100C8N - 芯片, FPGA, CYCLONE 2910, SMD; ·Up to 294912 RAM bits\n·Support for LVTTL, LVCMOS, SSTL-2 and SSTL-3 I/O standards\n·High-speed (640Mbps) LVDS I/O support\n·Low-speed (311Mbps) LVDS I/O support\n·311Mbps RSDS I/O support\n;

The EP1C3T100C8N is a surface mount Field Programmable Gate Array IC with PLL clock management and 2910 logic elements. The Cyclone? field programmable gate array with features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements. It support for multiple intellectual property (IP) cores, including Altera? MegaCore? functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.

EP1C3T100C8N

Package：100-TQFP；包裝：托盤 類別：集成電路（IC） FPGA（現(xiàn)場可編程門陣列） 描述：IC FPGA 65 I/O 100TQFP

EP1C3T100C8

CycloneFPGAFamily

EP1C3T100C8ES

CycloneFPGAFamilyDataSheet

Introduction TheCyclone?fieldprogrammablegatearrayfamilyisbasedona1.5-V,0.13-μm,all-layercopperSRAMprocess,withdensitiesupto20,060logicelements(LEs)andupto288KbitsofRAM.Withfeatureslikephase-lockedloops(PLLs)forclockingandadedicateddoubledatarate(DDR)