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EL4584C

Horizontal Genlock, 4 FSC

GeneralDescription TheEL4584CisaPLL(PhaseLockLoop)subsystem,designedforvideoapplicationsbutalsosuitableforgeneralpurposeuseupto36MHz.InavideoapplicationthisdevicegeneratesaTTL/CMOScompatiblePixelClock(ClkOut)whichisamultipleoftheTVHorizontalscanrat

EL4584C

Horizontal Genlock, 4 FSC;

EL4584CN

Horizontal genlock, 4 F sc; 36 MHz, general purpose PLL\n4FSCbased timing (use the EL4585 for 8 FSC)\nCompatible w/EL4583 Sync Separator\nVCXO, Xtal, or LC tank oscillator\nk2 ns jitter (VCXO)\nUser controlled PLL capture and lock\nCompatible with NTSC and PAL TV formats\n8 pre-programmed TV scan rate clock divisors\nSelectable external divide for custom ratios\nSingle 5V, low current operationApplications\nPixel Clock regeneration\nVideo compression engine (MPEG) clock generator\nVideo capture or digitization\nPIP (Picture in Picture) timing generator\nText or graphics overlay timing;

General Description\nThe EL4584C is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multi ple of the TV Horizontal scan rate, and phase locked to it.

EL4584CN

Horizontal Genlock, 4 FSC

GeneralDescription TheEL4584CisaPLL(PhaseLockLoop)subsystem,designedforvideoapplicationsbutalsosuitableforgeneralpurposeuseupto36MHz.InavideoapplicationthisdevicegeneratesaTTL/CMOScompatiblePixelClock(ClkOut)whichisamultipleoftheTVHorizontalscanrat

EL4584CN

Horizontal Genlock, 4FSC

TheEL4584isaPLL(PhaseLockLoop)subsystem,designedforvideoapplicationsbutalsosuitableforgeneralpurposeuseupto36MHz.Invideoapplications,thisdevicegeneratesaTTL/CMOScompatiblePixelClock(CLKOUT)whichisamultipleoftheTVhorizontalscanrateandphaselockedtoi

EL4584CN

Marking：EL4584CN；Package：16LdPDIP；Horizontal Genlock, 4FSC

TheEL4584isaPLL(PhaseLockLoop)subsystem,designedforvideoapplicationsbutalsosuitableforgeneralpurposeuseupto36MHz.Invideoapplications,thisdevicegeneratesaTTL/CMOScompatiblePixelClock(CLKOUT)whichisamultipleoftheTVhorizontalscanrateandphaselockedtoi

EL4584CS

Horizontal Genlock, 4 FSC

GeneralDescription TheEL4584CisaPLL(PhaseLockLoop)subsystem,designedforvideoapplicationsbutalsosuitableforgeneralpurposeuseupto36MHz.InavideoapplicationthisdevicegeneratesaTTL/CMOScompatiblePixelClock(ClkOut)whichisamultipleoftheTVHorizontalscanrat

EL4584CS

Horizontal Genlock, 4FSC

TheEL4584isaPLL(PhaseLockLoop)subsystem,designedforvideoapplicationsbutalsosuitableforgeneralpurposeuseupto36MHz.Invideoapplications,thisdevicegeneratesaTTL/CMOScompatiblePixelClock(CLKOUT)whichisamultipleoftheTVhorizontalscanrateandphaselockedtoi

EL4584CS

Marking：EL4584CS；Package：16LdSOIC；Horizontal Genlock, 4FSC

TheEL4584isaPLL(PhaseLockLoop)subsystem,designedforvideoapplicationsbutalsosuitableforgeneralpurposeuseupto36MHz.Invideoapplications,thisdevicegeneratesaTTL/CMOScompatiblePixelClock(CLKOUT)whichisamultipleoftheTVhorizontalscanrateandphaselockedtoi

EL4584CSZ

Horizontal Genlock, 4FSC

TheEL4584isaPLL(PhaseLockLoop)subsystem,designedforvideoapplicationsbutalsosuitableforgeneralpurposeuseupto36MHz.Invideoapplications,thisdevicegeneratesaTTL/CMOScompatiblePixelClock(CLKOUT)whichisamultipleoftheTVhorizontalscanrateandphaselockedtoi