描述 Description

?dsPIC33Fs are designed to execute digital filter algorithmsand high-speed precision digital control loops, ideal for applications thatneed to perform under pressure? ? ? ? ? ??GeneralPurpose Digital Signal Controllers (DSCs) with advanced analog and seamlessmigration options to PIC24F, PIC24H MCUs and dsPIC30F DSCs

特性 Features

Operating RangeUp to 40 MIPS operation (at 3.0-3.6V)
3.0V to 3.6V, -40oC to +150oC, DC to 20 MIPS
? 3.0V to 3.6V, -40oC to +125oC, DC to 40 MIPS
High-Performance dsPIC33FJ core
? Modified Harvard architecture
? C compiler optimized instruction set
? 24-bit wide instructions, 16-bit wide data path
? Linear program memory addressing up to 4M instruction words
? Linear data memory addressing up to 64 Kbytes
? Two 40-bit accumulators with rounding and saturation options
? Indirect, Modulo and Bit-reversed addressing modes
? 16 x 16 fractional/integer multiply operations
? 32/16 and 16/16 divide operations
Single-cycle multiply and accumulate (MAC) with accumulator write back and dual data fetch
? Single-cycle MUL plus hardware divide
? Up to ±16-bit shifts for up to 40-bit data
? On-chip Flash and SRAM
Direct Memory Access (DMA)
? 8-channel hardare DMA
? Up to 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA
? Most peripherals support DMA
Timers/Capture/Compare/PWM
? Up to five 16-bit and up to two 32-bit Timers/Counters
? One timer runs as a Real-Time Clock with an external 32.768 kHz oscillator
? Input Capture (up to four channels) with Capture on up, down or both edges
? 16-bit capture input functions
? 4-deep FIFO on each capture
? Output Compare (up to four channels) with Single or Dual 16-bit Compare mode and 16-bit Glitchless PWM mode
? Hardware Real-Time Clock/Calendar (RTCC)
Interrupt Controller
? 5-cycle latency
? 118 interrupt vectors
? Up to 49 available interrupt sources
? Up to three external interrups
? Seven programmable priority levels
? Five processor exceptions
Digital I/O
? Peripheral pin Select functionality
? Up to 35 programmable digital I/O pins
? Wake-up/Interrupt-on-Change for up to 21 pins
? Output pins can drive from 3.0V to 3.6V
? Up to 5V output with open drain configuration
? All digital input pins are 5V tolerant
? 4 mA sink on all I/O pins
System Management
? Flexible clock options: External, crystal, resonator and internal RC
? Fully integrated Phase-Locked Loop (PLL)
? Extremely low jitter PLL
? Power-up Timer
? Oscillator Start-up Timer/Stabilizer
? Watchdog Timer with its own RC oscillator
? Fail-Safe Clock Monitor
? Reset by multiple sources
Power ManagementOn-chip 2.5V voltage regulator
? Switch between clock sources in real time
? Idle, Sleep, and Doze modes with fast wake-up
Analog-to-Digital Converters (ADCs)10-bit, 11 Msps or 12-bit, 500 Ksps conversion
? Two and four simultaneous samples (10-bit ADC)
? Up to 13 input channels with auto-scanning
? Conversion start can be manual or synchronized with one of four trigger sources
? Conversion possible in Sleep mode
? ±2 LSb max integral nonlinearity
? ±1 LSb max differential nonlinearity
Other Analog Peripherals
? Two analog comparators with programmable input/output configuration
? 4-bit DAC with two ranges for analog comparators
? 16-bit dual channel 100 Ksps audio DAC
Data Converter Interface (DCI) module
? Codec interface
? Supports I2S and AC.97 protocols
? Up to 16-bit data words, up to 16 words per frame
? 4-word deep TX and RX buffers
Communication Modules
? 4-wire SPI (up to two modules) with I/O interface to simple codecs
? I2C? with Full Multi-Master Slave mode support, slave address masking, 7-bit and 10-bit addressing, integrated signal conditioning and bus collision detection
? UART (up to two modules) with LIN bus support, IrDA? and hardware flow control with CTS and RTS
Enhanced CAN (ECAN) module (1 Mbaud) with 2.0B support
? Parallel Master Slave Port (PMP/EPSP)
? Programmable Cyclic Redundancy Check (CRC)
Debugger Development Support
? In-circuit and in-application programming
? Two program breakpoints
? Trace and run-time watch