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DS92LX2121

10MHz 至 50MHz 直流平衡 Channel Link III 雙向控制串行器; ? General \n? Up to 1050 Mbits/sec Data Throughput\n? 10 MHz to 50 MHz Input Clock Support\n? Supports 18-bit Color Depth (RGB666 + HS, VS, DE)\n? Embedded Clock with DC Balanced Coding to Support AC-Coupled Interconnects\n? Capable to Drive up to 10 Meters Shielded Twisted-Pair\n? Bi-Directional Control Interface Channel with I2C Support\n? I2C Interface for Device Configuration. Single-Pin ID Addressing\n? Up to 4 GPI on DES and GPO on SER\n? AT-SPEED BIST Diagnosis Feature to Validate Link Integrity\n? Individual Power-Down Controls for both SER and DES\n? User-Selectable Clock Edge for Parallel Data on both SER and DES\n? Integrated Termination Resistors\n? 1.8V- or 3.3V-Compatible Parallel Bus Interface\n? Single Power Supply at 1.8V\n? IEC 61000–4–2 ESD Compliant\n? Temperature Range ?40°C to +85°C\n \n? DESERIALIZER — DS92LX2122 \n? No Reference Clock Required on Deserializer\n? Programmable Receive Equalization\n? LOCK Output Reporting Pin to Ensure\n? EMI/EMC Mitigation \n? Programmable Spread Spectrum (SSCG) Outputs\n? Receiver Output Drive Strength Control (RDS)\n? Receiver Staggered Outputs;

The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex control channel for data transmission over a single differential pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with a bi-directional back channel control bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bi-directional back channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional back channel control information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector size and pins.In addition, the Deserializer provides input equalization to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.A sleep function provides a power-savings mode when the high speed forward channel and embedded bi-directional control channel are not needed.The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages.

DS92LX2121

10 - 50 MHz Channel Link III Serializer and Deserializer with Embedded Bi-Directional Control Channel

DS92LX2121

10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121

10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121

DS92LX2121/DS92LX2122 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121_14

10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121_15

10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121SQ/NOPB

10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121SQE/NOPB

10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121SQESLASHNOPB

10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer