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DS92LV1212A

具有嵌入式時鐘恢復(fù)功能的 16 MHz - 40 MHz 10 位總線 LVDS 隨機(jī)鎖定解串器; ·Clock recovery without SYNC patterns-random lock\n ·Guaranteed transition every data transfer cycle\n ·Chipset (Tx + Rx) power consumption TRI-STATE? is a registered trademark of National Semiconductor Corporation.;

The DS92LV1212A is an upgrade of the DS92LV1212. It maintains all of the features of the DS92LV1212. The DS92LV1212A is designed to be used with the DS92LV1021 Bus LVDS Serializer. The DS92LV1212A receives a Bus LVDS serial data stream and transforms it into a 10-bit wide parallel data bus and separate clock. The reduced cable, PCB trace count and connector size saves cost and makes PCB layout easier. Clock-to-data and data-to-data skews are eliminated since one input receives both clock and data bits serially. The powerdown pin is used to save power by reducing the supply current when the device is not in use. The Deserializer will establish lock to a synchronization pattern within specified lock times but it can also lock to a data stream without SYNC patterns.\n \n

DS92LV1212A

16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

DS92LV1212A

DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

DS92LV1212A

The DS92LV 1212A is an upgrade of the DS92LV1212.

DS92LV1212AMSA

16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

DS92LV1212AMSA

DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

DS92LV1212AMSA/NOPB

The DS92LV 1212A is an upgrade of the DS92LV1212.

DS92LV1212AMSA/NOPB

DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

DS92LV1212AMSASLASHNOPB

The DS92LV 1212A is an upgrade of the DS92LV1212.

DS92LV1212AMSASLASHNOPB

DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery