DS90UA102TRHSJQ1屬于集成電路（IC）的串行器解串器。由美國(guó)德州儀器公司制造生產(chǎn)的DS90UA102TRHSJQ1串行器，解串器串行器將并行提供的信息轉(zhuǎn)換為較高符號(hào)率的串行數(shù)據(jù)流，從而減少數(shù)字信息傳輸所需的導(dǎo)線數(shù)量；解串器執(zhí)行相反的功能。常用于在圖像傳感器、圖像處理器和顯示器之間傳輸視頻數(shù)據(jù)，還有針對(duì)工業(yè) I/O 設(shè)備等其他應(yīng)用而定制的器件。

1FEATURES

? Digital Audio Deserializer

? Flexible Digital Audio Outputs, supporting I2S

(Stereo) and TDM (Multi-Channel) Formats

? Coaxial or Single Differential Pair Interconnect

? High Speed Serial Input Interface

? Very Low Latency (<15 μs)

? Bidirectional Control Interface Channel with

I2C Compatible Serial Control Bus

? Supports up to 8 Stereo I2S or TDM Audio

Outputs

? Supports Audio System Clocks from 10 MHz to

50 MHz

? Single 1.8V Supply

? 1.8V or 3.3V I/O Interface

? 4/4 Dedicated General Purpose Inputs/Outputs

? AC-Coupled STP or Coaxial Cable up to 15m

? DC-Balanced & Scrambled Data w/ Embedded

Clock

? Adaptive Cable Equalization

? At-Speed Link BIST Mode and LOCK Status

Pin

? Automotive Grade Product: AEC-Q100 Grade 2

Qualified

? Temperature Range: -40°C to 105°C

? ISO 10605 and IEC 61000-4-2 ESD Compliant

APPLICATIONS

? Automotive Infotainment Systems

? Active Noise Cancellation Systems

? Distributed Multi-Channel Audio Systems

DESCRIPTION

The DS90UA102-Q1 Deserializer, in conjunction with

the DS90UA101-Q1 Serializer, provides a solution for distribution of digital audio in multi-channel audio

systems. It receives a high-speed serialized interface

with an embedded clock over a single shielded

twisted pair or coaxial cable. The serial bus scheme

supports high speed forward data transmission and low speed bidirectional control channel over the link.

Consolidation of digital audio, general-purpose IO,

and control signals over a single differential pair

reduces the interconnect size and weight, while also

reducing design challenges related to skew and system latency.

The DS90UA102-Q1 Deserializer extracts the clock

and level shifts the signals from high-speed low voltage differential signaling to single-ended

LVCMOS. The device outputs up to eight digital audio

data channels, word/frame sync, bit clock, and

system clock.

Four dedicated general purpose input pins and four

general purpose output pins allow flexible

implementation of control and interrupt signals to and

from remote devices.

Adaptive equalization of the serial input stream

provides compensation for transmission medium

losses of the cable and reduces medium-induced

deterministic jitter.