DS90LV110AT屬于集成電路（IC）的時鐘緩沖器驅(qū)動器。由美國德州儀器公司制造生產(chǎn)的DS90LV110AT時鐘緩沖器，驅(qū)動器時鐘緩沖器和驅(qū)動器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時間參考信號，以同步系統(tǒng)內(nèi)的活動。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅(qū)動負載的影響而從某個信號源復(fù)制信號），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個整數(shù)值分割信號頻率，或進行所用電信號格式轉(zhuǎn)換。

1FEATURES

2? Low jitter 400 Mbps fully differential data path

? 145 ps (typ) of pk-pk jitter with PRBS = 223?1

data pattern at 400 Mbps

? Single +3.3 V Supply

? Balanced output impedance

? Output channel-to-channel skew is 35ps (typ)

? Differential output voltage (VOD) is 320mV (typ)

with 100Ω termination load.

? LVDS receiver inputs accept LVPECL signals

? LVDS input failsafe

? Fast propagation delay of 2.8 ns (typ)

? Receiver open, shorted, and terminated input

failsafe

? 28 lead TSSOP package

? Conforms to ANSI/TIA/EIA-644 LVDS standard

DESCRIPTION

DS90LV110A is a 1 to 10 data/clock distributor

utilizing LVDS (Low Voltage Differential Signaling)

technology for low power, high speed operation. Data

paths are fully differential from input to output for low

noise generation and low pulse width distortion. The

design allows connection of 1 input to all 10 outputs.

LVDS I/O enable high speed data transmission for

point-to-point interconnects. This device can be used

as a high speed differential 1 to 10 signal distribution

/ fanout replacing multi-drop bus applications for

higher speed links with improved signal quality. It can

also be used for clock distribution up to 200MHz.

The DS90LV110A accepts LVDS signal levels,

LVPECL levels directly or PECL with attenuation

networks.

The LVDS outputs can be put into TRI-STATE by use of the enable pin.

For more details, please refer to the APPLICATION

INFORMATION section of this datasheet.