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DS90C387

+3.3V 雙像素 LVDS 顯示接口 (LDI)-SVGA/QXGA 發(fā)送器; ? Complies with OpenLDI Specification for Digital Display Interfaces\n? 32.5 to 112/170MHz Clock Support for DS90C387, 40 to 112MHz Clock Support for DS90CF388\n? Supports SVGA through QXGA Panel Resolutions\n? Drives Long, Low Cost Cables\n? Up to 5.38Gbps Bandwidth\n? Pre-Emphasis Reduces Cable Loading Effects\n? DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion\n? Cable Deskew of +/?1 LVDS Data Bit Time (up to 80 MHz Clock Rate) of Pair-to-Pair Skew at Receiver Inputs; Intra-Pair Skew Tolerance of 300ps\n? Dual Pixel Architecture Supports Interface to GUI and Timing Controller; Optional Single Pixel Transmitter Inputs Support Single Pixel GUI Interface\n? Transmitter Rejects Cycle-to-Cycle Jitter\n? 5V Tolerant on Data and Control Input Pins\n? Programmable Transmitter Data and Control Strobe Select (Rising or Falling Edge Strobe)\n? Backward Compatible Configuration Select with FPD-Link\n? Optional Second LVDS Clock for Backward Compatibility w/ FPD-Link\n? Support for Two Additional User-Defined Control Signals in DC Balanced Mode\n? Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard;

The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential Signalling) data streams. Control signals (VSYNC, HSYNC, DE and two user-defined signals) are sent during blanking intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps, providing a total throughput of 5.38Gbps (672 Megabytes per second). Two other modes are also supported. 24-bit color data (single pixel) can be clocked into the transmitter at a maximum rate of 170MHz. In this mode, the transmitter provides single-to-dual pixel conversion, and the output LVDS clock rate is 85MHz maximum. The third mode provides inter-operability with FPD-Link devices. The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth, the maximum pixel clock rate is increased to 112 (170) MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew of up to +/?1 LVDS data bit time (up to 80 MHz Clock Rate). These three enhancements allow cables 5+ meters in length to be driven. This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to .

DS90C387

Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

DS90C387

Dual Pixel LVDS Display Interface (LDI)=SVGA/QXGA

DS90C387A

雙像素 LVDS 顯示接口/FPD 鏈接發(fā)送器; ? Supports SVGA through QXGA panel resolutions\n? 32.5 to 112/170MHz clock support\n? Drives long, low cost cables\n? Up to 5.7 Gbps bandwidth\n? Pre-emphasis reduces cable loading effects\n? Dual pixel architecture supports interface to GUI and timing controller; optional single pixel transmitter inputs support single pixel GUI interface\n? Transmitter rejects cycle-to-cycle jitter\n? 5V tolerant on data and control input pins\n? Programmable transmitter data and control strobe select (rising or falling edge strobe)\n? Backward compatible with FPD-Link\n? Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard\n TRI-STATE? is a registered trademark of National Semiconductor Corporation.;

The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second). \n\n The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. \n\n The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit FPD-Link receivers.\n\n This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the \"Applications Information\" section of this datasheet.\n\n \n\n The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second). \n\n The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. \n\n The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit FPD-Link receivers.\n\n This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the \"Applications Information\" section of this datasheet.\n\n \n\n

DS90C387R

85MHz 雙路 12 位雙泵輸入 LDI 發(fā)送器 VGA/UXGA; ? Complies with Open LDI Specification for Digital Display Interfaces\n? 25 to 85MHz Clock Support\n? Supports VGA through UXGA Panel Resolution\n? Up to 4.76Gbps Bandwidth in Dual 24-bit RGB In-to-Dual Pixel Out Application\n? Dual 12-bit Double Pumped Input DVO Port\n? Pre-Emphasis Reduces Cable Loading Effects\n? Drives Long, Low Cost Cables\n? DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion\n? Transmitter Rejects Cycle-to-Cycle Jitter (±2ns of Input Bit Period)\n? Support both LVTTL and Low Voltage Level Input (Capable of 1.0 to 1.8V)\n? Two-Wire Serial Communication Interface up to 400 KHz\n? Programmable Input Clock and Control Strobe Select\n? Backward Compatible Configuration with 112MHz LDI and FPD-Link\n? Optional Second LVDS Clock for Backward Compatibility with FPD-Link Receivers\n? Compatible with TIA/EIA-644\n;

The DS90C387R transmitter is designed to support pixel data transmission from a Host to a Flat Panel Display up to UXGA resolution. It is designed to be compatible with Graphics Memory Controller Hub (GMCH) by implementing two data per clock and can be controlled by a two-wire serial communication interface. Two input modes are supported: one port of 12-bit( two data per clock) input for 24-bit RGB, and two ports of 12-bit( two data per clock) input for dual 24-bit RGB( 48-bit total). In both modes, input data will be clocked on both rising and falling edges in LVTTL level operation, or clocked on the cross over of differential clock signals in the low swing operation. Each input data width will be 1/2 of clock cycle. With an input clock at 85MHz and input data at 170Mbps, the maximum transmission rate of each LVDS line is 595Mbps, for a aggregate throughput rate of 2.38Gbps/4.76Gbps. It converts 24/48 bits (Single/Dual Pixel 24-bit color) of data into 4/8 LVDS (Low Voltage Differential Signaling) data streams. DS90C387R can be programmed via the two-wire serial communication interface. The LVDS output pin-out is identical to DS90C387. Thus, this transmitter can be paired up with DS90CF388, receiver of the 112MHz LDI chipset or FPD-Link Receivers in non-DC Balance mode operation which provides GUI/LCD panel/mother board vendors a wide choice of inter-operation with LVDS based TFT panels.\nDS90C387R also comes with features that can be found on DS90C387. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. DC Balancing on a cycle-to-cycle basis is also provided to reduce ISI (Inter-Symbol Interference), control signals (VSYNC, HSYNC, DE) are sent during blanking intervals. With pre-emphasis and DC Balancing, a low distortion eye-pattern is provided at the receiver end of the cable. These enhancements allow cables 5 to 15+ meters in length to be driven depending on media characteristic and pixel clock speed. Pre-emphasis is available in both the DC Balanced and Non-DC Balanced modes. In the Non-DC Balanced mode backward compatibility with FPD-Link Receivers is obtained.\n This chip is an ideal solution to solve EMI and cable size problems for high-resolution flat panel display applications. It provides a reliable industry standard interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the “Applications Information” section of this datasheet.\n \n

DS90C387_06

Dual Pixel LVDS Display Interface (LDI)=SVGA/QXGA

DS90C387_15

Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

DS90C387A

Dual Pixel LVDS Display Interface / FPD-Link

DS90C387A

Dual Pixel LVDS Display Interface/FPD-Link

DS90C387A

Dual Pixel LVDS Display Interface / FPD-Link