特性 Features

? DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation
? Pin and SMBus Configurable, Fully Differential, Non-Blocking Architecture
? Pin (Two Levels) and SMBus (Four Levels) Selectable Pre-Emphasis and Equalization Eliminate ISI Jitter
? Wide Input Common Mode Range Enables Easy Interface to CML and LVPECL Drivers
? LOS Circuitry Detects Open Inputs Fault Condition
? On-Chip 100? Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, Minimizes Board Space The DS25CP114 Eliminates the On-Chip Input Termination for Added Design Flexibility.
? 8 kV ESD on LVDS I/O Pins Protects Adjoining Components
? Small 6 mm x 6 mm WQFN-40 Space Saving Package