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DS25BR100

DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2?DC-3.125GbpsLowJitter,HighNoise Immunity,LowPowerOperation ?ReceiveEqualizationReducesISIJitterDueto MediaLoss ?TransmitPre-EmphasisDrivesLossy BackplanesandCables ?On-Chip100ΩInputandOutputTermination: –MinimizesInsertionandReturnLosses –R

DS25BR100

具有發(fā)送預(yù)加重和接收均衡功能的 3.125Gbps LVDS 緩沖器; ? DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation\n? Receive Equalization Reduces ISI Jitter Due to Media Loss\n? Transmit Pre-Emphasis Drives Lossy Backplanes and Cables\n? On-Chip 100? Input and Output Termination: \n? Minimizes Insertion and Return Losses\n? Reduces Component Count\n? Minimizes Board Space\n \n? DS25BR101 Eliminates On-Chip Input Termination for Added Design Flexibility\n? 7 kV ESD on LVDS I/O Pins Protects Adjoining Components\n? Small 3 mm x 3 mm WSON-8 Space Saving Package;

The DS25BR100 and DS25BR101 are single channel 3.125 Gbps LVDS buffers optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.The DS25BR100 and DS25BR101 feature transmit pre-emphasis (PE) and receive equalization (EQ), making them ideal for use as a repeater device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR110 features four levels of equalization for use as an optimized receiver device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. On the DS25BR100 the differential input and output is internally terminated with a 100? resistor to lower return losses, reduce component count and further minimize board space. For added design flexibility the 100? input terminations on the DS25BR101 have been eliminated. This elimination enables a designer to adjust the termination for custom interconnect topologies and layout.

DS25BR100

3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

DS25BR100

3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

DS25BR100

3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

DS25BR100

3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

DS25BR100TSD/NOPB

絲?。?a target="_blank" title="Marking" href="/2r100/marking.html">2R100；Package：WSON；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2?DC-3.125GbpsLowJitter,HighNoise Immunity,LowPowerOperation ?ReceiveEqualizationReducesISIJitterDueto MediaLoss ?TransmitPre-EmphasisDrivesLossy BackplanesandCables ?On-Chip100ΩInputandOutputTermination: –MinimizesInsertionandReturnLosses –R

DS25BR100TSD/NOPB.A

絲印：2R100；Package：WSON；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2?DC-3.125GbpsLowJitter,HighNoise Immunity,LowPowerOperation ?ReceiveEqualizationReducesISIJitterDueto MediaLoss ?TransmitPre-EmphasisDrivesLossy BackplanesandCables ?On-Chip100ΩInputandOutputTermination: –MinimizesInsertionandReturnLosses –R

DS25BR100TSDSLASHNOPB

絲?。?a target="_blank" title="Marking" href="/2r100/marking.html">2R100；Package：WSON；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2?DC-3.125GbpsLowJitter,HighNoise Immunity,LowPowerOperation ?ReceiveEqualizationReducesISIJitterDueto MediaLoss ?TransmitPre-EmphasisDrivesLossy BackplanesandCables ?On-Chip100ΩInputandOutputTermination: –MinimizesInsertionandReturnLosses –R

DS25BR100TSDSLASHNOPB.A

絲?。?a target="_blank" title="Marking" href="/2r100/marking.html">2R100；Package：WSON；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2?DC-3.125GbpsLowJitter,HighNoise Immunity,LowPowerOperation ?ReceiveEqualizationReducesISIJitterDueto MediaLoss ?TransmitPre-EmphasisDrivesLossy BackplanesandCables ?On-Chip100ΩInputandOutputTermination: –MinimizesInsertionandReturnLosses –R