描述 Description

Specifically designed for use in low-power systems, the DS1033 has three independent, buffered delays that reproduce logic inputs after delays ranging from 8ns to 30ns at each output. Characterized for operating over the 2.7V to 3.6V range, nominal tolerance is ±1.5ns with additional tolerance of ±1.0ns over temperature and voltage for faster delays (see table). Both leading- and trailing-edge accuracy are specified. Each output can drive up to ten 74LS loads.
The DS1033 brings the benefits of an all-silicon delay circuit to new low-voltage systems. Dallas delay lines provide an effective, economical solution to the designer working with the complex timing requirements of mismatched ASICs or other components, or with the strict timing tolerances of increasing system clock rates. Besides fine-tuning system timing, the DS1033 can also function as a pulse width modulator or free-running oscillator. Innovative circuit designs and factory laser or EPROM trimming enhance accuracy without the need for external components, saving cost and space.

特性 Features

? All-silicon timing circuit
? Three independent, buffered delays
? Delay range at each output: 8ns to 30ns
? Initial delay tolerance ±1.5ns
? Stable and precise over temperature and voltage
? Leading and trailing edge precision
? Vapor phase, IR, and wave solderable
? Voltage operating range: 2.7V to 3.6V

簡(jiǎn)介

DS1033屬于集成電路（IC）的延遲線。由制造生產(chǎn)的DS1033延遲線時(shí)鐘延遲線產(chǎn)品族中的產(chǎn)品屬于數(shù)字器件，用于在數(shù)字信號(hào)中引入時(shí)間延遲，以便將提交給器件輸入的信號(hào)躍遷，經(jīng)過某一已知時(shí)間之后在輸出端復(fù)現(xiàn)。它們常用于高速數(shù)字系統(tǒng)，以校正或補(bǔ)償不同信號(hào)路徑之間的信號(hào)傳播時(shí)間的偏差。這些器件可用于產(chǎn)生固定、可選或可變持續(xù)時(shí)間的延遲。