描述 Description

The DS1021 is an 8-bit programmable delay line that reproduces an input logic state at the output after a user-programmed delay. It is similar to the DS1020 but with the economy of reduced specifications. Available in two versions, total delays are varied over 256 steps and range from an inherent 10ns minimum delay in both versions to a maximum delay of 137.5ns. The DS1021 can be programmed over the 3-wire serial port or the 8-pin parallel port. The DS1021 is TTL- and CMOS-compatible and capable of driving up to ten 74LS-type loads. Both leading- and trailing-edge accuracy are specified.
The DS1021 is an effective, economical solution to the designer working with the complex timing requirements of mismatched ASICs or other components, or with the strict timing tolerances of increasing system clock rates. With the DS1021's programmable outputs, the user can precisely adjust timing to application needs and improve system performance. Innovative circuit designs and factory laser or EPROM trimming enhance accuracy without the need for external components, saving cost and space.

特性 Features

? All-silicon time delay
? Models with 0.25ns and 0.5ns steps
? Programmable using 3-wire serial port or 8-bit parallel port
? Leading and trailing edge accuracy
? Auto-insertable, low profile
? Low-power CMOS with TTL compatibility
? Vapor phase, IR, and wave solderable

簡(jiǎn)介

DS1021屬于集成電路（IC）的延遲線。由制造生產(chǎn)的DS1021延遲線時(shí)鐘延遲線產(chǎn)品族中的產(chǎn)品屬于數(shù)字器件，用于在數(shù)字信號(hào)中引入時(shí)間延遲，以便將提交給器件輸入的信號(hào)躍遷，經(jīng)過(guò)某一已知時(shí)間之后在輸出端復(fù)現(xiàn)。它們常用于高速數(shù)字系統(tǒng)，以校正或補(bǔ)償不同信號(hào)路徑之間的信號(hào)傳播時(shí)間的偏差。這些器件可用于產(chǎn)生固定、可選或可變持續(xù)時(shí)間的延遲。