GENERAL DESCRIPTION

The DM9006 is a fully integrated and cost-effective fast Ethernet switch controller with two ports

10M/100M PHY, and general processor bus interface. The integrated two ports PHY are compliant

with IEEE 802.3u standards and support HP Auto-MDIX capabilities for twisted-pair cable

transmit/receive direction automatic switching. The general processor bus can be configured as 8-bit or 16-bit data width.

The DM9006 is a managed Switch, not only provides basic Layer-2 switch functions but offers advanced features that include 802.1Q VLAN, priority queuing management, bandwidth rate control, monitoring port traffic, multicast packet filtering, port security and hardware-based IGMP V1/V2 Snooping, etc.

FEATURES

? Ethernet Switch with two 10/100Mb PHY, and a flexible 8-bit or 16-bit general processor bus interface

? Store and Forward switching approach

? Support HP Auto-MDIX

? Support up-to 1K Unicast MAC addresses

? Support IEEE 802.3x Flow Control in Full-duplex mode

? Support Back Pressure Flow Control in Half-duplex mode

? Per port supports ingress or egress bandwidth rate control

? Support Broadcast/Multicast Storm Suppression

? Support maximum packet length up to 1536(default)/2032 bytes

? Support head of Line (HOL) blocking prevention

? Support MIB counters for diagnostic

? General processor bus is slave architecture

? General processor bus driving capability is adjustable

? General processor bus supports TCP/UDP/IPv4 checksum offload

? EEPROM interface for power up configuration

? Support EEPROM 93C46/93C56 with auto-detecting

? Driving capability of TXD/TXE of MII is adjustable

? Per port supports 4 level priority queues by Port-based, 802.1p VLAN, and IP TOS priority.

The priority queue can be set at WRR(Weighted Round Robin) or Strictly(High priority queue first)

? Support 802.1Q VLAN up-to 16 VLAN group.

? Support VLAN ID tag/untag options

? MAC Address Table is accessible

? Support 256-entry multicast address table

? Support port security function

? Support 32 entry hardware-based IGMP Snooping V1, V2

? uP data driving capability adjustable

? 64-pin LQFP 1.8V internal core, 3.3V I/O with 5V tolerant

? Support Lead-Free and Halogen–Free