KEY FEATURES

? Double Data Rate (DDR) architecture: two data transfers per clock cycle

? High-speed data transfer is realized by 8 bits prefetch pipelined architecture

? Bi-directional differential data strobe (DOS and /DQS) is transmitted/received

with data for capturing data at the receiver

? DOS is edge-aligned with data for READS; center-aligned with data for WRITES

? Differential clock inputs (CK and /CK)

? DLL aligns DQ and DOS transitions with CK transitions

? Commands entered on each positive CK edge; data and data mask referenced

to both edges of DQS

? Data Mask (DM) for write data

? Posted /CAS by programmable additive latency for better command and data

bus efficiency

? On-Die Termination (ODD for better signal quality)

o Synchronous ODT

o Dynamic CDT

o Asynchronous ODT

? Multi-Purpose Register (MPR) for pre-defined pattern read out

? ZQ calibration for DO drive and ODT

? Programmable Partial Array Self-Refresh (PASR)

? RESET pin for power-up sequence and reset function

? SRT range: normal/extended

? Programmable output driver impedance control