General Description

With its unique array of configurable blocks, PSoC? 3 is a true ystem level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

特性 Features

■ Single cycle 8051 CPU core

□ DC to 50 MHz operation

□ Multiply and divide instructions

□ Flash program memory, up to 64 KB, 100,000 write cycles, 20 years retention, and multiple security features

□ Up to 8-KB flash error correcting code (ECC) or configuration storage

□ Up to 8 KB SRAM

□ Up to 2 KB electrically erasable programmable read-only memory (EEPROM), 1 M cycles, and 20 years retention

□ 24-channel direct memory access (DMA) with multilayer AHB[1] bus access

? Programmable chained descriptors and priorities

? High bandwidth 32-bit transfer support

■ Low voltage, ultra low-power

□ Wide operating voltage range: 0.5 V to 5.5 V

□ High efficiency boost regulator from 0.5-V through 1.8-V to 5.0-V output

□ 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz

□ Low-power modes including:

? 1-μA sleep mode with real-time clock (RTC) and low-voltage detect (LVD) interrupt

? 200-nA hibernate mode with RAM retention

■ Versatile I/O system

□ 28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO), two USBIOs[2])

□ Any GPIO to any digital or analog peripheral routability

□ LCD direct drive from any GPIO, up to 46×16 segments[2]

□ CapSense? support from any GPIO[3]

□ 1.2-V to 5.5-V I/O interface voltages, up to four domains

□ Maskable, independent IRQ on any pin or port

□ Schmitt-trigger transistor-transistor logic (TTL) inputs

□ All GPIO configurable as open drain high/low, pull-up/pull-down, High Z, or strong output

□ Configurable GPIO pin state at power-on reset (POR)

□ 25 mA sink on SIO

■ Digital peripherals

□ 16 to 24 programmable PLD based universal digital blocks (UDB)

□ Full-speed (FS) USB 2.0 12 Mbps using internal oscillator[2]

□ Up to four 16-bit configurable timer, counter, and PWM blocks

□ Library of standard peripherals

? 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

? Serial peripheral interface (SPI), universal asynchronous transmitter receiver (UART), and I2C

? Many others available in catalog

□ Library of advanced peripherals

? Cyclic redundancy check (CRC)

? Pseudo random sequence (PRS) generator

? Local interconnect network (LIN) bus 2.0

? Quadrature decoder

■ Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)

□ 1.024 V ±0.9-percent internal voltage reference across –40°C to +85°C (14 ppm/°C)

□ Configurable delta-sigma ADC with 8- to12-bit resolution

? Programmable gain stage: ×0.25 to ×16

? 12-bit mode, 192-ksps, 66-dB signal to noise and distortion ratio (SINAD), ±1-bit INL/DNL

□ One 8-bit, 8-Msps IDAC or 1-Msps VDAC

□ Two comparators with 95 ns response time

□ CapSense support

■ Programming, debug, and trace

□ JTAG (4-wire), serial wire debug (SWD) (2-wire), and single wire viewer (SWV) interfaces

□ Eight address and one data breakpoint

□ 4-KB instruction trace buffer

□ Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces

■ Precision, programmable clocking

□ 3- to 24-MHz internal oscillator over full temperature and voltage range

□ 4- to 25-MHz crystal oscillator for crystal PPM accuracy

□ Internal PLL clock generation up to 50 MHz

□ 32.768-kHz watch crystal oscillator

□ Low-power internal oscillator at 1, 33, and 100 kHz

■ Temperature and packaging

□ –40°C to +85°C degrees industrial temperature

□ 48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP package options