Functional Description[1]

The CY7C1324H is a 128K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

特性 Features

? 128K x 18 common I/O

? 3.3V core power supply

? 3.3V/2.5V I/O supply

? Fast clock-to-output times

— 6.5 ns (133-MHz version)

? Provide high-performance 2-1-1-1 access rate

? User-selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed write

? Asynchronous output enable

? Offered in JEDEC-standard lead-free 100-pin TQFP package

? “ZZ” Sleep Mode option