CY74FCT273TSOC屬于集成電路（IC）的觸發(fā)器。由美國德州儀器公司制造生產(chǎn)的CY74FCT273TSOC觸發(fā)器觸發(fā)器是能夠存儲單個邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個輸入；一個或多個用于傳遞要存儲的數(shù)據(jù)，另一個用于指示存儲該數(shù)據(jù)的時間點。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對提供給其輸入的信號有不同的響應(yīng)，可用于實現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時鐘信號時才會改變。

Function, Pinout, and Drive Compatible

With FCT and F Logic

Reduced VOH (Typically = 3.3 V) Versions

of Equivalent FCT Functions

Edge-Rate Control Circuitry for

Significantly Improved Noise

Characteristics

Ioff Supports Partial-Power-Down Mode

Operation

Matched Rise and Fall Times

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

Fully Compatible With TTL Input and

Output Logic Levels

CY54FCT273T

– 32-mA Output Sink Current

– 12-mA Output Source Current

CY74FCT273T

– 64-mA Output Sink Current

– 32-mA Output Source Current

description

The ’FCT273T devices consist of eight

edge-triggered D-type flip-flops with individual

D inputs and Q outputs. The common

buffered-clock (CP) and master-reset (MR) inputs

load and reset all flip-flops simultaneously. These

devices are edge-triggered registers. The state of

each D input (one setup time before the

low-to-high clock transition) is transferred to the

corresponding flip-flop’s Q output. All outputs are

forced low by a low logic level on the MR input.

This device is fully specified for

partial-power-down applications using Ioff. The Ioff

circuitry disables the outputs, preventing

damaging current backflow through the device

when it is powered down.